Abstract: Semiconductor devices (e.g., gate-all-around (GAA) devices), process tools for manufacturing GAA devices and methods of manufacturing GAA devices, and inner spacer liners and inner spacers for GAA devices, are described. The methods comprise performing a chemical vapor deposition (CVD) process to form an amorphous silicon liner and an inner spacer within a superlattice structure formed on a top surface of a semiconductor substrate. The superlattice structure has a plurality of semiconductor material layers (e.g., silicon germanium (SiGe)) and a corresponding plurality of channel layers (e.g., silicon (Si)). The amorphous silicon liner is conformally formed along the GAA device, including along the recessed semiconductor material layers and the corresponding plurality of channel layers, and the inner spacer is formed directly on the amorphous silicon liner. One or more operations of the methods described herein are performed in situ in an integrated processing tool system.

Abstract: A method of increasing thermal uniformity of a substrate incorporates high thermal conductivity material in place of shallow trench isolation (STI) dielectric material or interlayer dielectric (ILD) material on a backside of a thinned substrate. The method may comprise removing at least a portion of an STI dielectric material and/or ILD material and depositing a second dielectric material in place of the STI dielectric material that is removed. The second dielectric material has a higher thermal conductivity than the STI dielectric material. The removal may incorporate a wet or dry etch process that is selective to the STI dielectric material and/or the ILD material over other materials used in formation of semiconductor structures on a substrate.

Abstract: The embodiments herein provide thermal processing apparatus. The thermal processing apparatus includes a radiation module configured to generate a line of radiation for an annealing process, a substrate support configured to receive a substrate thereon, and a translation mechanism. The substrate support includes one or more channels configured to flow a working fluid therethrough. The working fluid is configured to enable a bottom surface of the substrate disposed upon the substrate support to be cooled to a temperature of about 200° C. to about ?200° C. during the annealing process. The translation mechanism is configured to translate the substrate support and the line of radiation relative to one another.

Abstract: A method for forming a structure with a backside power delivery network incorporates a high thermal conductivity material as the bonding layer. In some embodiments, the method may comprise forming a first layer stack that includes a front side metallization (FSM) signal layer formed on a silicon die layer containing nano-through silicon vias (n-TSVs) that is formed on a back side metallization (BSM) power distribution layer where the n-TSVs provide back side power connections to the FSM signal layer, forming a second layer stack that includes a silicon carrier layer, and forming a third layer stack that includes the first layer stack and the second layer stack bonded together with a bonding layer interposed between the first layer stack and the second layer stack where the bonding layer is formed of a cubic-boron nitride-based material.

Abstract: Printable resin precursor compositions and polishing articles including printable resin precursors are provided that are particularly suited for polishing substrates utilized in hybrid bonding applications. Methods and articles may include a plurality of first polishing elements, where at least one of the plurality of first polymer layers forms the polishing surface; and one or more second polishing elements, where at least a region of each of the one or more second polishing elements is disposed between at least one of the plurality of first polishing elements and a supporting surface of the polishing pad. One or more first polishing elements have a Shore D hardness of greater than 60, one or more second polishing elements have a Shore D hardness of from about 20 to less than 60, and the polishing article has a total Shore D hardness of greater than or about 50.

Abstract: Methods and structures to achieve low voltage (LV) and high voltage (HV) scale-down by suppressing the short channel effect of LV as well as increasing breakdown voltage of HV transistor are provided. A semiconductor device comprises a first transistor comprising a first well region of a first conductivity type, a first gate region disposed above the first well region, and a first contact region including a first epitaxial semiconductor adjacent to the first gate region; and a second transistor comprising a second well region of a second conductivity, a second gate region disposed above the second well region, and a second contact region including a second epitaxial semiconductor adjacent to the second gate region.

Abstract: Semiconductor devices (e.g., gate-all-around (GAA) devices), process tools for manufacturing GAA devices and methods of manufacturing GAA devices, and inner spacer liners and inner spacers for GAA devices, are described. The methods comprise performing a chemical vapor deposition (CVD) process to form an amorphous silicon liner and an inner spacer within a superlattice structure formed on a top surface of a semiconductor substrate. The superlattice structure has a plurality of semiconductor material layers (e.g., silicon germanium (SiGe)) and a corresponding plurality of channel layers (e.g., silicon (Si)). The amorphous silicon liner is conformally formed along the GAA device, including along the recessed semiconductor material layers and the corresponding plurality of channel layers, and the inner spacer is formed directly on the amorphous silicon liner. One or more operations of the methods described herein are performed in situ in an integrated processing tool system.

Abstract: Semiconductor devices (e.g., gate-all-around (GAA) devices), process tools for manufacturing GAA devices and methods of manufacturing GAA devices, and inner spacer liners and inner spacers for GAA devices, are described. The methods comprise forming an inner spacer liner within a superlattice structure formed on a top surface of a semiconductor substrate. The superlattice structure has a plurality of recessed semiconductor material layers (e.g., silicon germanium (SiGe)) and a corresponding plurality of channel layers (e.g., silicon (Si)) alternatingly arranged in a plurality of stacked pairs. The inner spacer liner comprises a crystalline silicon-containing liner formed by a selective epitaxial growth (SEG) process. The crystalline silicon-containing liner may be doped with a dopant (e.g., a p-type dopant or an n-type dopant). One or more operations of the methods described herein are performed in situ in an integrated processing tool system.

Abstract: Semiconductor devices (e.g., gate-all-around (GAA) devices), process tools for manufacturing GAA devices and methods of manufacturing GAA devices and multilayer inner spacers for GAA devices are described. The multilayer inner spacer comprises an inner layer, a middle layer, and an outer layer within a superlattice structure formed on a top surface of a substrate. The superlattice structure has a plurality of semiconductor material layers (e.g., silicon germanium (SiGe)) and a corresponding plurality of channel layers (e.g., silicon (Si)) alternatingly arranged in a plurality of stacked pairs. In some embodiments, the methods are performed in situ in an integrated deposition and etch processing system.

Abstract: A method for forming alignment marks leverages pad density and critical dimensions (CDs). In some embodiments, the method includes forming first and second alignment marks on a first substrate and a second substrate where the alignment marks have a width within 5% of the associated CD of copper pads on the respective substrates and forming a first and second dummy patterns around the first and second alignment marks. The first and second dummy patterns have dummy pattern densities within 5% of the respective copper pad density of the first and second substrates and CDs within 5% of the respective copper pad CDs. In some embodiments, alignment marks with physical dielectric material protrusions and recesses on opposite substrate surfaces may further enhance bonding.

Abstract: A method for forming alignment marks leverages pad density and critical dimensions (CDs). In some embodiments, the method includes forming first and second alignment marks on a first substrate and a second substrate where the alignment marks have a width within 5% of the associated CD of copper pads on the respective substrates and forming a first and second dummy patterns around the first and second alignment marks. The first and second dummy patterns have dummy pattern densities within 5% of the respective copper pad density of the first and second substrates and CDs within 5% of the respective copper pad CDs. In some embodiments, alignment marks with physical dielectric material protrusions and recesses on opposite substrate surfaces may further enhance bonding.

Abstract: A method and related structure provide a void-free dielectric over trench isolation region in an FDSOI substrate. The structure may include a first transistor including a first active gate over the substrate, a second transistor including a second active gate over the substrate, a first liner extending over the first transistor, and a second, different liner extending over the second transistor. A trench isolation region electrically isolates the first transistor from the second transistor. The trench isolation region includes a trench isolation extending into the FDSOI substrate and an inactive gate over the trench isolation. A dielectric extends over the inactive gate and in direct contact with an upper surface of the trench isolation region. The dielectric is void-free, and the liners do not extend over the trench isolation.

Abstract: A semiconductor device is provided that includes an active region above a substrate, a first gate structure, a second gate structure, a first semiconductor structure, a second semiconductor structure and a semiconductor bridge. The first gate semiconductor and the second semiconductor structure are in the active region and between the first and the second gate structures. The first semiconductor structure is adjacent to the first gate structure and a second semiconductor structure is adjacent to the second gate structure. The semiconductor bridge is in the active region electrically coupling the first and the second semiconductor structures.

Abstract: A semiconductor device is provided, which includes an active region, a first structure, a second gate structure, a first gate dielectric sidewall, a second gate dielectric sidewall, a first air gap region, a second air gap region and a contact structure. The active region is formed over a substrate. The first and second gate structures are formed over the active region and between the first gate structure and the second gate structure are the first gate dielectric sidewall, the first air gap region, the contact structure, the second air gap region and a second gate dielectric sidewall.

Abstract: A method and related structure provide a void-free dielectric over trench isolation region in an FDSOI substrate. The structure may include a first transistor including a first active gate over the substrate, a second transistor including a second active gate over the substrate, a first liner extending over the first transistor, and a second, different liner extending over the second transistor. A trench isolation region electrically isolates the first transistor from the second transistor. The trench isolation region includes a trench isolation extending into the FDSOI substrate and an inactive gate over the trench isolation. A dielectric extends over the inactive gate and in direct contact with an upper surface of the trench isolation region. The dielectric is void-free, and the liners do not extend over the trench isolation.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a single diffusion break device and methods of manufacture. The structure includes a single diffusion break structure with a fill material between sidewall spacers of the single diffusion break structure and a channel oxidation below the fill material.

Abstract: A semiconductor device is provided, which includes an active region, a first structure, a second gate structure, a first gate dielectric sidewall, a second gate dielectric sidewall, a first air gap region, a second air gap region and a contact structure. The active region is formed over a substrate. The first and second gate structures are formed over the active region and between the first gate structure and the second gate structure are the first gate dielectric sidewall, the first air gap region, the contact structure, the second air gap region and a second gate dielectric sidewall.

Abstract: A semiconductor device is provided that includes an active region above a substrate, a first gate structure, a second gate structure, a first semiconductor structure, a second semiconductor structure and a semiconductor bridge. The first gate semiconductor and the second semiconductor structure are in the active region and between the first and the second gate structures. The first semiconductor structure is adjacent to the first gate structure and a second semiconductor structure is adjacent to the second gate structure. The semiconductor bridge is in the active region electrically coupling the first and the second semiconductor structures.

Abstract: One illustrative method disclosed herein may include forming a first straight sidewall spacer adjacent a gate structure of a transistor, forming a recessed layer of sacrificial material adjacent the first straight sidewall spacer and forming a second straight sidewall spacer on a portion of the outer surface of the first straight sidewall spacer and above the recessed layer of sacrificial material. The method may also include removing the recessed layer of sacrificial material so as to expose a first vertical portion of the outer surface of the first straight sidewall spacer and forming an epi material on and above the substrate, wherein an edge of the epi material engages the first straight sidewall spacer.

Abstract: A FinFET structure having reduced effective capacitance and including a substrate having at least two fins thereon laterally spaced from one another, a metal gate over fin tops of the fins and between sidewalls of upper portions of the fins, source/drain regions in each fin on opposing sides of the metal gate, and a dielectric bar within the metal gate located between the sidewalls of the upper portions of the fins, the dielectric bar being laterally spaced away from the sidewalls of the upper portions of the fins within the metal gate.