Abstract: A system may receive a frame, divide the frame into objects, select an object from the objects, divide the object into regions, determine a set of attributes for a target region of the regions, assign a priority to the target region, and queue, based on an assignment of a low priority, the target region to a discount rendering instance.

Abstract: A method includes: receiving, by a processor set, context data from one or more Internet of Things (IoT) sensors; identifying, by the processor set, one or more objects in a frame of a video stream, thereby determining identified objects; classifying, by the processor set, the identified objects, thereby determining classified objects; prioritizing, by the processor set, the classified objects using the context data, thereby determining prioritized objects; selecting, by the processor set, an object from the prioritized objects; enhancing, by the processor set, the frame of the video stream based on the selected object; and rendering, by the processor set, the enhanced frame on a display of a visual enhancement device.

Abstract: A computer-implemented method, computer program product, and/or computing system is disclosed for preforming at least one of a performance group consisting of undoing an action in and uninstalling a software application from a computing environment is disclosed. The computer-implemented method, computer program product, and/or computing system includes: building an initial resource dependency graph; building a second resource dependency graph; determining a resulting resource dependency graph to identify dangling resources; and removing the dangling resources. In an embodiment, building at least one of the initial resource dependency graph or the second resource dependency graph includes building a resource ownership graph and extending the resource ownership graph to include associations to form a resource dependency graph.

Abstract: An integrated sensor package for an electronic device may include a matrix material defining a body structure of the integrated sensor package, a light emitting diode at least partially encapsulated in the matrix material, a photodiode at least partially encapsulated in the matrix material and configured to detect light emitted by the light emitting diode and reflected by an object external to the integrated sensor package, a via structure at least partially encapsulated in the matrix material, a permanent magnet at least partially encapsulated in the matrix material, a first conductive member on a first side of the integrated sensor package and conductively coupling the light emitting diode to a first end of the via structure, and a second conductive member on a second side of the integrated sensor package opposite the first side and conductively coupled to a second end of the via structure.

Abstract: The present invention is designed so that uplink control information such as delivery acknowledgment signals can be transmitted properly, even when UL/DL configurations are changed, in a communication system that is configured to use listening. According to one aspect of the present invention, a user terminal has a receiving section that receives downlink control information and downlink data, a transmission section that transmits a delivery acknowledgment signal in response to the downlink data, and a control section that controls transmission of the delivery acknowledgment signal based on a result of UL listening which is executed before transmission of the delivery acknowledgment signal, and based on information that is contained in the downlink control information and/or timing that is configured in advance on a per DL burst basis.

Abstract: A display panel and a display device are disclosed. The display panel includes a first substrate, a second substrate, and a liquid crystal layer disposed therebetween. The first substrate includes a first base and a planarization layer disposed on a side of the first substrate adjacent to the liquid crystal layer. A side of the planarization layer adjacent to the liquid crystal layer includes a textured structure, which includes at least one groove path. The first substrate further includes a bottom edge. An extending direction of the at least one groove path forms an included angle with the bottom edge, the included angle being greater than or equal to 45 degrees and less than or equal to 135 degrees. A liquid crystal material in the liquid crystal layer diffuses along the extending direction of the groove path through the groove path based on capillary phenomenon.

Abstract: Heat pipes and vapor chambers that are components of a DIMM cooling assembly are described.

Abstract: Immersion cooling systems, apparatus, and related methods for cooling electronic computing platforms and/or associated electronic components are disclosed herein. An example apparatus includes a first chamber including a first coolant disposed therein, the first coolant having a first boiling point. The example apparatus further includes a second chamber disposed in the first chamber, the second chamber to receive an electronic component therein. The second chamber includes a second coolant having a second boiling point different that the first boiling point. The second chamber is to separate the electronic component and the second coolant from the first coolant.

Abstract: This disclosure relates to a lipid-based topical injection formulation containing a Long-Acting SusTained delivering lipid, a structured lipid, a polymer-conjugated lipid and an ionizable lipid, and optionally a neutral phospholipid. The lipid-based topical injection formulation enables enriched delivery of drugs at an injection site and efficient expression of proteins for a prolonged period of time. This disclosure also relates to a method of preparing the lipid-based topical injection formulation, and use of the lipid-based topical injection formulation in the delivery of biologically active substances such as nucleic acids (e.g., mRNA, miRNA, siRNA, saRNA, ASO, DNA, etc.).

Abstract: Aspects of the present disclosure relate to data visualization in web conferences. Type-related information of a web conference can be acquired. A conference type of the web conference can be identified based on the acquired type-related information of the web conference and type templates stored in a type repository. A visualization format from a plurality of visualization formats stored in a format repository can be determined based on the identified conference type. Key information required by the determined visualization format can be extracted from raw data of the web conference. Visual data within the determined visual format can be created by populating the extracted key information into the determined visualization format.

Abstract: Semiconductor devices (e.g., gate-all-around (GAA) devices), process tools for manufacturing GAA devices and methods of manufacturing GAA devices, and inner spacer liners and inner spacers for GAA devices, are described. The methods comprise performing a chemical vapor deposition (CVD) process to form an amorphous silicon liner and an inner spacer within a superlattice structure formed on a top surface of a semiconductor substrate. The superlattice structure has a plurality of semiconductor material layers (e.g., silicon germanium (SiGe)) and a corresponding plurality of channel layers (e.g., silicon (Si)). The amorphous silicon liner is conformally formed along the GAA device, including along the recessed semiconductor material layers and the corresponding plurality of channel layers, and the inner spacer is formed directly on the amorphous silicon liner. One or more operations of the methods described herein are performed in situ in an integrated processing tool system.

Abstract: Semiconductor devices (e.g., gate-all-around (GAA) devices), process tools for manufacturing GAA devices and methods of manufacturing GAA devices, and inner spacer liners and inner spacers for GAA devices, are described. The methods comprise forming an inner spacer liner within a superlattice structure formed on a top surface of a semiconductor substrate. The superlattice structure has a plurality of recessed semiconductor material layers (e.g., silicon germanium (SiGe)) and a corresponding plurality of channel layers (e.g., silicon (Si)) alternatingly arranged in a plurality of stacked pairs. The inner spacer liner comprises a crystalline silicon-containing liner formed by a selective epitaxial growth (SEG) process. The crystalline silicon-containing liner may be doped with a dopant (e.g., a p-type dopant or an n-type dopant). One or more operations of the methods described herein are performed in situ in an integrated processing tool system.

Abstract: Semiconductor devices (e.g., gate-all-around (GAA) devices), process tools for manufacturing GAA devices and methods of manufacturing GAA devices and multilayer inner spacers for GAA devices are described. The multilayer inner spacer comprises an inner layer, a middle layer, and an outer layer within a superlattice structure formed on a top surface of a substrate. The superlattice structure has a plurality of semiconductor material layers (e.g., silicon germanium (SiGe)) and a corresponding plurality of channel layers (e.g., silicon (Si)) alternatingly arranged in a plurality of stacked pairs. In some embodiments, the methods are performed in situ in an integrated deposition and etch processing system.

Abstract: A method for forming alignment marks leverages pad density and critical dimensions (CDs). In some embodiments, the method includes forming first and second alignment marks on a first substrate and a second substrate where the alignment marks have a width within 5% of the associated CD of copper pads on the respective substrates and forming a first and second dummy patterns around the first and second alignment marks. The first and second dummy patterns have dummy pattern densities within 5% of the respective copper pad density of the first and second substrates and CDs within 5% of the respective copper pad CDs. In some embodiments, alignment marks with physical dielectric material protrusions and recesses on opposite substrate surfaces may further enhance bonding.

Abstract: A method for forming alignment marks leverages pad density and critical dimensions (CDs). In some embodiments, the method includes forming first and second alignment marks on a first substrate and a second substrate where the alignment marks have a width within 5% of the associated CD of copper pads on the respective substrates and forming a first and second dummy patterns around the first and second alignment marks. The first and second dummy patterns have dummy pattern densities within 5% of the respective copper pad density of the first and second substrates and CDs within 5% of the respective copper pad CDs. In some embodiments, alignment marks with physical dielectric material protrusions and recesses on opposite substrate surfaces may further enhance bonding.

Abstract: A method and related structure provide a void-free dielectric over trench isolation region in an FDSOI substrate. The structure may include a first transistor including a first active gate over the substrate, a second transistor including a second active gate over the substrate, a first liner extending over the first transistor, and a second, different liner extending over the second transistor. A trench isolation region electrically isolates the first transistor from the second transistor. The trench isolation region includes a trench isolation extending into the FDSOI substrate and an inactive gate over the trench isolation. A dielectric extends over the inactive gate and in direct contact with an upper surface of the trench isolation region. The dielectric is void-free, and the liners do not extend over the trench isolation.

Abstract: A semiconductor device is provided that includes an active region above a substrate, a first gate structure, a second gate structure, a first semiconductor structure, a second semiconductor structure and a semiconductor bridge. The first gate semiconductor and the second semiconductor structure are in the active region and between the first and the second gate structures. The first semiconductor structure is adjacent to the first gate structure and a second semiconductor structure is adjacent to the second gate structure. The semiconductor bridge is in the active region electrically coupling the first and the second semiconductor structures.

Abstract: A semiconductor device is provided, which includes an active region, a first structure, a second gate structure, a first gate dielectric sidewall, a second gate dielectric sidewall, a first air gap region, a second air gap region and a contact structure. The active region is formed over a substrate. The first and second gate structures are formed over the active region and between the first gate structure and the second gate structure are the first gate dielectric sidewall, the first air gap region, the contact structure, the second air gap region and a second gate dielectric sidewall.

Abstract: A method and related structure provide a void-free dielectric over trench isolation region in an FDSOI substrate. The structure may include a first transistor including a first active gate over the substrate, a second transistor including a second active gate over the substrate, a first liner extending over the first transistor, and a second, different liner extending over the second transistor. A trench isolation region electrically isolates the first transistor from the second transistor. The trench isolation region includes a trench isolation extending into the FDSOI substrate and an inactive gate over the trench isolation. A dielectric extends over the inactive gate and in direct contact with an upper surface of the trench isolation region. The dielectric is void-free, and the liners do not extend over the trench isolation.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a single diffusion break device and methods of manufacture. The structure includes a single diffusion break structure with a fill material between sidewall spacers of the single diffusion break structure and a channel oxidation below the fill material.