Patents by Inventor Liu JIANG
Liu JIANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967646Abstract: Disclosed are a thin film transistor structure, a display panel and a display device. The thin film transistor structure includes a base, a source electrode, a drain electrode configured to connect to a pixel electrode and a grid electrode. The source electrode, the drain electrode and the grid electrode are provided on the base. and a channel is formed between the source electrode and the drain electrode. The thin film transistor structure further includes an insulating layer and a slow-release electrode. The insulating layer is provided on a side of the source electrode and the drain electrode, and filled in the channel. The slow-release electrode is provided in the insulating layer. At least a part of the slow-release electrode is provided inside the channel.Type: GrantFiled: June 1, 2023Date of Patent: April 23, 2024Assignee: HKC CORPORATION LIMITEDInventors: Keming Yang, Yizhen Xu, Chunhui Ren, Feng Jiang, Liu He, Qiang Leng, Rongrong Li
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Patent number: 11956759Abstract: A terminal is disclosed including a selection unit that selects first resource candidates for sidelink transmission based on monitoring in a sensing window, and specifies second resource candidates by excluding specific periodic resources that are reserved by another terminal from the first resource candidates; and a transmission unit that performs sidelink transmission using a resource selected from the second resource candidates. In another aspect, a transmission method executed by a terminal is also disclosed.Type: GrantFiled: July 12, 2021Date of Patent: April 9, 2024Assignee: NTT DOCOMO, INC.Inventors: Shinpei Yasukawa, Satoshi Nagata, Qun Zhao, Jing Wang, Huan Wang, Liu Liu, Anxin Li, Huiling Jiang
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Publication number: 20240103896Abstract: A computer-implemented method, system and computer program product for scaling a resource of a Database as a Service (DBaaS) cluster in a cloud platform. User service requests from a service cluster to be processed by the DBaaS cluster are received. A first set of tracing data is generated by a service mesh, which facilitates service-to-service communication between the service cluster and the DBaaS cluster, from the user service requests. A second set of tracing data is generated by the DBaaS cluster from handling the user service requests. A dependency tree is then generated to discover application relationships to identify potential bottlenecks in nodes of the DBaaS cluster based on these sets of tracing data. The pod(s) of a DBaaS node are then scaled based on the dependency tree, which is used in part, to predict the utilization of the resources of the DBaaS node identified as being a potential bottleneck.Type: ApplicationFiled: September 24, 2022Publication date: March 28, 2024Inventors: Peng Hui Jiang, Yue Wang, Jun Su, Su Liu, Sheng Yan Sun
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Patent number: 11940991Abstract: An indication to remove one or more data in a time series database is received. A metadata index associated with the time series database is updated to indicate a soft removal of each data of the one or more data. A data hole index associated with the time series database is updated to indicate a data hole at a location of each data of the one or more data in the time series database. Responsive to an input/output rate for the time series database being below a threshold, the data hole of each data of the one or more data is optimized.Type: GrantFiled: March 22, 2021Date of Patent: March 26, 2024Assignee: International Business Machines CorporationInventors: Huai Long Zhang, Peng Hui Jiang, Jin Shan Li, Rui Liu, Ming Lei Zhang
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Publication number: 20240088298Abstract: Disclosed are a thin film transistor structure, a display panel and a display device. The thin film transistor structure includes a base, a source electrode, a drain electrode configured to connect to a pixel electrode and a grid electrode. The source electrode, the drain electrode and the grid electrode are provided on the base. and a channel is formed between the source electrode and the drain electrode. The thin film transistor structure further includes an insulating layer and a slow-release electrode. The insulating layer is provided on a side of the source electrode and the drain electrode, and filled in the channel. The slow-release electrode is provided in the insulating layer. At least a part of the slow-release electrode is provided inside the channel.Type: ApplicationFiled: June 1, 2023Publication date: March 14, 2024Applicant: HKC CORPORATION LIMITEDInventors: Keming YANG, Yizhen XU, Chunhui REN, Feng JIANG, Liu HE, Qiang LENG, Rongrong LI
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Patent number: 11930620Abstract: There is disclosed in one example a heat dissipator for an electronic apparatus, including: a planar vapor chamber having a substantially rectangular form factor, wherein a second dimension d2 of the rectangular form factor is at least approximately twice a first dimension d1 of the rectangular form factor; a first fan and second fan; and a first heat pipe and second heat pipe discrete from the planar vapor chamber and disposed along first and second d1 edges of the planar vapor chamber, further disposed to conduct heat from the first and second d1 edges to the first and second fan respectively.Type: GrantFiled: June 27, 2020Date of Patent: March 12, 2024Assignee: Intel CorporationInventors: Jeff Ku, Cora Nien, Gavin Sung, Tim Liu, Lance Lin, Wan Yu Liu, Gerry Juan, Jason Y. Jiang, Justin M. Huttula, Evan Piotr Kuklinski, Juha Tapani Paavola, Arnab Sen, Hari Shanker Thakur, Prakash Kurma Raju
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Publication number: 20240069448Abstract: A method for forming alignment marks leverages pad density and critical dimensions (CDs). In some embodiments, the method includes forming first and second alignment marks on a first substrate and a second substrate where the alignment marks have a width within 5% of the associated CD of copper pads on the respective substrates and forming a first and second dummy patterns around the first and second alignment marks. The first and second dummy patterns have dummy pattern densities within 5% of the respective copper pad density of the first and second substrates and CDs within 5% of the respective copper pad CDs. In some embodiments, alignment marks with physical dielectric material protrusions and recesses on opposite substrate surfaces may further enhance bonding.Type: ApplicationFiled: August 31, 2022Publication date: February 29, 2024Inventors: Prayudi LIANTO, Liu JIANG, Marvin Louis BERNT, El Mehdi BAZIZI, Guan Huei SEE
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Patent number: 11917773Abstract: An embodiment of a barrier assembly includes a housing having an aperture and a magnet at least partially disposed within the housing. A first surface of the magnet is exposed. The barrier assembly also includes a light-emitting component disposed within the aperture. Another embodiment of a barrier assembly includes a housing having a plurality of apertures formed about a perimeter of the housing. The barrier assembly also includes a magnet at least partially embedded within the housing and the magnet includes an opening formed through a center of the magnet and a plurality of light-emitting components, each light-emitting component at least partially disposed within a corresponding aperture of the plurality of apertures.Type: GrantFiled: December 1, 2021Date of Patent: February 27, 2024Assignee: Apple, Inc.Inventors: Saijin Liu, Tongbi T. Jiang
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Patent number: 11899376Abstract: A method for forming alignment marks leverages pad density and critical dimensions (CDs). In some embodiments, the method includes forming first and second alignment marks on a first substrate and a second substrate where the alignment marks have a width within 5% of the associated CD of copper pads on the respective substrates and forming a first and second dummy patterns around the first and second alignment marks. The first and second dummy patterns have dummy pattern densities within 5% of the respective copper pad density of the first and second substrates and CDs within 5% of the respective copper pad CDs. In some embodiments, alignment marks with physical dielectric material protrusions and recesses on opposite substrate surfaces may further enhance bonding.Type: GrantFiled: August 31, 2022Date of Patent: February 13, 2024Assignee: APPLIED MATERIALS, INC.Inventors: Prayudi Lianto, Liu Jiang, Marvin Louis Bernt, El Mehdi Bazizi, Guan Huei See
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Patent number: 11171036Abstract: A method and related structure provide a void-free dielectric over trench isolation region in an FDSOI substrate. The structure may include a first transistor including a first active gate over the substrate, a second transistor including a second active gate over the substrate, a first liner extending over the first transistor, and a second, different liner extending over the second transistor. A trench isolation region electrically isolates the first transistor from the second transistor. The trench isolation region includes a trench isolation extending into the FDSOI substrate and an inactive gate over the trench isolation. A dielectric extends over the inactive gate and in direct contact with an upper surface of the trench isolation region. The dielectric is void-free, and the liners do not extend over the trench isolation.Type: GrantFiled: October 9, 2019Date of Patent: November 9, 2021Assignee: GlobalFoundries U.S. Inc.Inventors: Yongjun Shi, Wei Hong, Chun Yu Wong, Halting Wang, Liu Jiang
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Patent number: 11164794Abstract: A semiconductor device is provided that includes an active region above a substrate, a first gate structure, a second gate structure, a first semiconductor structure, a second semiconductor structure and a semiconductor bridge. The first gate semiconductor and the second semiconductor structure are in the active region and between the first and the second gate structures. The first semiconductor structure is adjacent to the first gate structure and a second semiconductor structure is adjacent to the second gate structure. The semiconductor bridge is in the active region electrically coupling the first and the second semiconductor structures.Type: GrantFiled: August 4, 2019Date of Patent: November 2, 2021Assignee: GLOBALFOUNDRIES U.S. Inc.Inventors: Wei Hong, Liu Jiang, Yanping Shen
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Patent number: 11018221Abstract: A semiconductor device is provided, which includes an active region, a first structure, a second gate structure, a first gate dielectric sidewall, a second gate dielectric sidewall, a first air gap region, a second air gap region and a contact structure. The active region is formed over a substrate. The first and second gate structures are formed over the active region and between the first gate structure and the second gate structure are the first gate dielectric sidewall, the first air gap region, the contact structure, the second air gap region and a second gate dielectric sidewall.Type: GrantFiled: August 12, 2019Date of Patent: May 25, 2021Assignee: GLOBALFOUNDRIES U.S. Inc.Inventors: Chun Yu Wong, Haiting Wang, Yong Jun Shi, Xiaoming Yang, Liu Jiang
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Publication number: 20210111065Abstract: A method and related structure provide a void-free dielectric over trench isolation region in an FDSOI substrate. The structure may include a first transistor including a first active gate over the substrate, a second transistor including a second active gate over the substrate, a first liner extending over the first transistor, and a second, different liner extending over the second transistor. A trench isolation region electrically isolates the first transistor from the second transistor. The trench isolation region includes a trench isolation extending into the FDSOI substrate and an inactive gate over the trench isolation. A dielectric extends over the inactive gate and in direct contact with an upper surface of the trench isolation region. The dielectric is void-free, and the liners do not extend over the trench isolation.Type: ApplicationFiled: October 9, 2019Publication date: April 15, 2021Inventors: Yongjun Shi, Wei Hong, Chun Yu Wong, Haiting Wang, Liu Jiang
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Patent number: 10957578Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a single diffusion break device and methods of manufacture. The structure includes a single diffusion break structure with a fill material between sidewall spacers of the single diffusion break structure and a channel oxidation below the fill material.Type: GrantFiled: September 28, 2018Date of Patent: March 23, 2021Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Wei Hong, Hui Zang, Hsien-Ching Lo, Zhenyu Hu, Liu Jiang
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Publication number: 20210050412Abstract: A semiconductor device is provided, which includes an active region, a first structure, a second gate structure, a first gate dielectric sidewall, a second gate dielectric sidewall, a first air gap region, a second air gap region and a contact structure. The active region is formed over a substrate. The first and second gate structures are formed over the active region and between the first gate structure and the second gate structure are the first gate dielectric sidewall, the first air gap region, the contact structure, the second air gap region and a second gate dielectric sidewall.Type: ApplicationFiled: August 12, 2019Publication date: February 18, 2021Inventors: Chun Yu WONG, Haiting Wang, Yong Jun Shi, Xiaoming Yang, Liu Jiang
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Publication number: 20210035869Abstract: A semiconductor device is provided that includes an active region above a substrate, a first gate structure, a second gate structure, a first semiconductor structure, a second semiconductor structure and a semiconductor bridge. The first gate semiconductor and the second semiconductor structure are in the active region and between the first and the second gate structures. The first semiconductor structure is adjacent to the first gate structure and a second semiconductor structure is adjacent to the second gate structure. The semiconductor bridge is in the active region electrically coupling the first and the second semiconductor structures.Type: ApplicationFiled: August 4, 2019Publication date: February 4, 2021Inventors: WEI HONG, LIU JIANG, YANPING SHEN
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Patent number: 10825897Abstract: One illustrative method disclosed herein may include forming a first straight sidewall spacer adjacent a gate structure of a transistor, forming a recessed layer of sacrificial material adjacent the first straight sidewall spacer and forming a second straight sidewall spacer on a portion of the outer surface of the first straight sidewall spacer and above the recessed layer of sacrificial material. The method may also include removing the recessed layer of sacrificial material so as to expose a first vertical portion of the outer surface of the first straight sidewall spacer and forming an epi material on and above the substrate, wherein an edge of the epi material engages the first straight sidewall spacer.Type: GrantFiled: January 30, 2019Date of Patent: November 3, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Wei Hong, George R. Mulfinger, Hui Zang, Liu Jiang, Zhenyu Hu
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Patent number: 10797049Abstract: A FinFET structure having reduced effective capacitance and including a substrate having at least two fins thereon laterally spaced from one another, a metal gate over fin tops of the fins and between sidewalls of upper portions of the fins, source/drain regions in each fin on opposing sides of the metal gate, and a dielectric bar within the metal gate located between the sidewalls of the upper portions of the fins, the dielectric bar being laterally spaced away from the sidewalls of the upper portions of the fins within the metal gate.Type: GrantFiled: October 25, 2018Date of Patent: October 6, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Hui Zang, Haiting Wang, Chung Foong Tan, Guowei Xu, Ruilong Xie, Scott H. Beasor, Liu Jiang
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Patent number: 10777642Abstract: One illustrative method disclosed herein may include forming a first straight sidewall spacer adjacent a gate structure of a transistor, forming a second straight sidewall spacer on the first straight sidewall spacer and forming a recessed layer of sacrificial material adjacent the second straight sidewall spacer such that the recessed layer of sacrificial material covers an outer surface of a first vertical portion of the second straight sidewall spacer while exposing a second vertical portion of the second straight sidewall spacer. In this example, the method may also include removing the second vertical portion of the second straight sidewall spacer, removing the recessed layer of sacrificial material and forming an epi material such that an edge of the epi material engages the outer surface of the first vertical portion of the second straight sidewall spacer.Type: GrantFiled: January 30, 2019Date of Patent: September 15, 2020Assignee: GLOBALFOUNDRIES Inc.Inventors: Wei Hong, George R. Mulfinger, Hui Zang, Liu Jiang, Zhenyu Hu
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Patent number: 10756184Abstract: The present disclosure relates to semiconductor structures and, more particularly, to faceted epitaxial source/drain regions and methods of manufacture. The structure includes: a gate structure over a substrate; an L-shaped sidewall spacer located on sidewalls of the gate structure and extending over the substrate adjacent to the gate structure; and faceted diffusion regions on the substrate, adjacent to the L-shaped sidewall spacer.Type: GrantFiled: November 5, 2018Date of Patent: August 25, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: George R. Mulfinger, Timothy J. McArdle, Judson R. Holt, Steffen A. Sichler, Ömür I. Aydin, Wei Hong, Yi Qi, Hui Zang, Liu Jiang