Patents by Inventor Liu Yaocheng

Liu Yaocheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CMOS structure including differential channel stressing layer compositions
    Patent number: 7875511
    Abstract: A CMOS structure includes an n-FET device comprising an n-FET channel region and a p-FET device comprising a p-FET channel region. The n-FET channel region includes a first silicon material layer located upon a silicon-germanium alloy material layer. The p-FET channel includes a second silicon material layer located upon a silicon-germanium-carbon alloy material layer. The silicon-germanium alloy material layer induces a desirable tensile strain within the n-FET channel. The silicon-germanium-carbon alloy material layer suppresses an undesirable tensile strain within the p-FET channel region. A silicon-germanium-carbon alloy material from which is comprised the silicon-germanium-carbon alloy material layer may be formed by selectively incorporating carbon into a silicon-germanium alloy material from which is formed the silicon-germanium alloy material layer.
    Type: Grant
    Filed: March 13, 2007
    Date of Patent: January 25, 2011
    Assignee: International Business Machines Corporation
    Inventors: Liu Yaocheng, Ricardo A. Donaton, Kern Rim