Patents by Inventor Livio Baldi

Livio Baldi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210151116
    Abstract: A method of forming a memory device having magnetic tracks individually comprising a plurality of magnetic domains having domain walls, includes forming an elevationally outer substrate material of uniform chemical composition. The uniform composition material is partially etched into to form alternating regions of elevational depressions and elevational protrusions in the uniform composition material. A plurality of magnetic tracks is formed over and which angle relative to the alternating regions. Interfaces of immediately adjacent of the regions individually form a domain wall pinning site in individual of the magnetic tracks. Other methods, including memory devices independent of method, are disclosed.
    Type: Application
    Filed: January 28, 2021
    Publication date: May 20, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Livio Baldi, Marcello Mariani
  • Patent number: 10923205
    Abstract: A method of forming a memory device having magnetic tracks individually comprising a plurality of magnetic domains having domain walls, includes forming an elevationally outer substrate material of uniform chemical composition. The uniform composition material is partially etched into to form alternating regions of elevational depressions and elevational protrusions in the uniform composition material. A plurality of magnetic tracks is formed over and which angle relative to the alternating regions. Interfaces of immediately adjacent of the regions individually form a domain wall pinning site in individual of the magnetic tracks. Other methods, including memory devices independent of method, are disclosed.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: February 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Livio Baldi, Marcello Mariani
  • Publication number: 20190019566
    Abstract: A method of forming a memory device having magnetic tracks individually comprising a plurality of magnetic domains having domain walls, includes forming an elevationally outer substrate material of uniform chemical composition. The uniform composition material is partially etched into to form alternating regions of elevational depressions and elevational protrusions in the uniform composition material. A plurality of magnetic tracks is formed over and which angle relative to the alternating regions. Interfaces of immediately adjacent of the regions individually form a domain wall pinning site in individual of the magnetic tracks. Other methods, including memory devices independent of method, are disclosed.
    Type: Application
    Filed: August 31, 2018
    Publication date: January 17, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Livio Baldi, Marcello Mariani
  • Patent number: 10147497
    Abstract: A method of forming a memory device having magnetic tracks individually comprising a plurality of magnetic domains having domain walls, includes forming an elevationally outer substrate material of uniform chemical composition. The uniform composition material is partially etched into to form alternating regions of elevational depressions and elevational protrusions in the uniform composition material. A plurality of magnetic tracks is formed over and which angle relative to the alternating regions. Interfaces of immediately adjacent of the regions individually form a domain wall pinning site in individual of the magnetic tracks. Other methods, including memory devices independent of method, are disclosed.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: December 4, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Livio Baldi, Marcello Mariani
  • Publication number: 20150235713
    Abstract: A method of forming a memory device having magnetic tracks individually comprising a plurality of magnetic domains having domain walls, includes forming an elevationally outer substrate material of uniform chemical composition. The uniform composition material is partially etched into to form alternating regions of elevational depressions and elevational protrusions in the uniform composition material. A plurality of magnetic tracks is formed over and which angle relative to the alternating regions. Interfaces of immediately adjacent of the regions individually form a domain wall pinning site in individual of the magnetic tracks. Other methods, including memory devices independent of method, are disclosed.
    Type: Application
    Filed: May 1, 2015
    Publication date: August 20, 2015
    Inventors: Livio Baldi, Marcello Mariani
  • Patent number: 9048410
    Abstract: A method of forming a memory device having magnetic tracks individually comprising a plurality of magnetic domains having domain walls, includes forming an elevationally outer substrate material of uniform chemical composition. The uniform composition material is partially etched into to form alternating regions of elevational depressions and elevational protrusions in the uniform composition material. A plurality of magnetic tracks is formed over and which angle relative to the alternating regions. Interfaces of immediately adjacent of the regions individually form a domain wall pinning site in individual of the magnetic tracks. Other methods, including memory devices independent of method, are disclosed.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: June 2, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Livio Baldi, Marcello Mariani
  • Publication number: 20140353781
    Abstract: A method of forming a memory device having magnetic tracks individually comprising a plurality of magnetic domains having domain walls, includes forming an elevationally outer substrate material of uniform chemical composition. The uniform composition material is partially etched into to form alternating regions of elevational depressions and elevational protrusions in the uniform composition material. A plurality of magnetic tracks is formed over and which angle relative to the alternating regions. Interfaces of immediately adjacent of the regions individually form a domain wall pinning site in individual of the magnetic tracks. Other methods, including memory devices independent of method, are disclosed.
    Type: Application
    Filed: May 31, 2013
    Publication date: December 4, 2014
    Inventors: Livio Baldi, Marcello Mariani
  • Patent number: 7820504
    Abstract: Embodiments of this invention relate to a method for manufacturing isolation structures with different depths in a monolithically integrated semiconductor electronic device. An inventive method according to an embodiment of the invention comprises a first step of defining active areas on a semiconductor material substrate, a second step of forming isolation structures by realising trenches in said substrate and then filling them with field oxide, a third step of defining lithographically at least a first device area, and a fourth step of realising a digging in the substrate and in the field oxide of said first device area.
    Type: Grant
    Filed: July 12, 2004
    Date of Patent: October 26, 2010
    Inventors: Daniela Brazzelli, Livio Baldi, Giorgio Servalli
  • Patent number: 7125807
    Abstract: A semiconductor substrate has active areas bounded by portions of an insulating layer. A thin layer of tunnel oxide is formed on the substrate and a first layer of conductive material is then deposited. Non-volatile memory cells are manufactured thereon by defining floating gate regions. The definition of these floating gate regions involves defining the first layer of conductive material in order to form a plurality of alternated stripes above pairs of active areas alternated by active areas lacking stripes. Spacers are then formed in the shelter of the side walls of the alternated stripes. A second layer of conductive material is then deposited together with the first layer of conductive material. The spacers are then selectively removed.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: October 24, 2006
    Assignee: STMicroelectronics S.r.l.
    Inventors: Cesare Clementi, Alessia Pavan, Livio Baldi
  • Patent number: 7125808
    Abstract: A method is described for manufacturing non-volatile memory cells on a semiconductive substrate having active areas bounded by portions of an insulating layer. A thin layer of tunnel oxide is formed and a first layer of conductive material is then deposited. A plurality of floating gate regions are defined by forming stripes of shielding material only above pairs of alternated active areas. Spacers of a selective material are defined with respect to the shielding material and of small width at will in the shelter of the side walls of the stripes thus defined. A shielding material is also deposited on the active areas which lacked it. The formation of the floating gate is completed by leaving the definition of the distance between the floating gate regions to the spacers.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: October 24, 2006
    Assignee: STMicroelectronics S.r.l.
    Inventors: Cesare Clementi, Alessia Pavan, Livio Baldi
  • Publication number: 20050042812
    Abstract: Embodiments of this invention relate to a method for manufacturing isolation structures with different depths in a monolithically integrated semiconductor electronic device. An inventive method according to an embodiment of the invention comprises a first step of defining active areas on a semiconductor material substrate, a second step of forming isolation structures by realising trenches in said substrate and then filling them with field oxide, a third step of defining lithographically at least a first device area, and a fourth step of realising a digging in the substrate and in the field oxide of said first device area.
    Type: Application
    Filed: July 12, 2004
    Publication date: February 24, 2005
    Inventors: Daniela Brazzelli, Livio Baldi, Giorgio Servalli
  • Patent number: 6812531
    Abstract: Matrix of memory cells formed using a method allowing for a self-alignment of the respective source region with the respective field oxide layer and the respective overlying polysilicon layer of each single cell of the matrix, the matrix including at least one first ROM memory cell suitable for permanently storing a first logic level, associated with a respective row and a respective column of the matrix, the first cell including a silicon substrate of a first conductivity type over which a first isolation region and a second isolation region are formed delimiting therebetween a longitudinal stripe, a gate element extending transversally through the stripe from at least one side of the first isolation region to at least one side of the second isolation region, a third region of a second conductivity type and a fourth region of a second conductivity type formed in the substrate along the stripe, and a field oxide region adapted to prevent the formation of a conductive channel in the substrate, and at least a s
    Type: Grant
    Filed: April 30, 1999
    Date of Patent: November 2, 2004
    Assignee: STMicroelectronics S.r.l.
    Inventors: Livio Baldi, Paolo Ghezzi
  • Publication number: 20040209472
    Abstract: A method is described for manufacturing non-volatile memory cells on a semiconductive substrate having active areas bounded by portions of an insulating layer. A thin layer of tunnel oxide is formed and a first layer of conductive material is then deposited. A plurality of floating gate regions are defined by forming stripes of shielding material only above pairs of alternated active areas. Spacers of a selective material are defined with respect to the shielding material and of small width at will in the shelter of the side walls of the stripes thus defined. A shielding material is also deposited on the active areas which lacked it. The formation of the floating gate is completed by leaving the definition of the distance between the floating gate regions to the spacers.
    Type: Application
    Filed: December 29, 2003
    Publication date: October 21, 2004
    Applicant: STMicroelectronics S.r.l.
    Inventors: Cesare Clementi, Alessia Pavan, Livio Baldi
  • Publication number: 20040203250
    Abstract: A semiconductor substrate has active areas bounded by portions of an insulating layer. A thin layer of tunnel oxide is formed on the substrate and a first layer of conductive material is then deposited. Non-volatile memory cells are manufactured thereon by defining floating gate regions. The definition of these floating gate regions involves defining the first layer of conductive material in order to form a plurality of alternated stripes above pairs of active areas alternated by active areas lacking stripes. Spacers are then formed in the shelter of the side walls of the alternated stripes. A second layer of conductive material is then deposited together with the first layer of conductive material. The spacers are then selectively removed.
    Type: Application
    Filed: December 23, 2003
    Publication date: October 14, 2004
    Applicant: STMicroelectronics S.r.l.
    Inventors: Cesare Clementi, Alessia Pavan, Livio Baldi
  • Publication number: 20040188757
    Abstract: A method for forming structures self-aligned with each other on a semiconductor substrate, comprising the following steps: Forming, on the semiconductor substrate, first regions of a first material projecting from the semiconductor substrate; forming, over the whole of the semiconductor substrate, a protective layer of a second material selective with respect to the first material; removing the protective layer to expose said first regions through a planarizing step; etching said first regions to expose said semiconductor substrate, and forming second regions projecting from the substrate of said protective layer. Advantageously, spacers are formed on the sidewalls of the first regions.
    Type: Application
    Filed: December 30, 2003
    Publication date: September 30, 2004
    Inventors: Livio Baldi, Cesare Clementi, Alessia Pavan
  • Publication number: 20040179392
    Abstract: A non-volatile memory cell is described, being integrated on a semiconductor substrate and comprising: A floating gate transistor including a source region and a drain region, a gate region projecting from the substrate and comprised between the source and drain regions, the gate region having a predetermined length and width and comprising a first floating gate region and a control gate region, in which the floating gate region is insulated laterally, along the width direction, by a dielectric layer with low dielectric constant value. A process for manufacturing non-volatile memory cells on a semiconductor substrate is also described, comprising the following steps: form active areas in the semiconductor substrate bounded by an insulating layer, deposit a first conductor material layer on active areas, define through a standard photolithographic technique a plurality of floating gate regions, form a dielectric layer with low dielectric constant value on the floating gate regions.
    Type: Application
    Filed: December 30, 2003
    Publication date: September 16, 2004
    Inventors: Alessia Pavan, Cesare Clementi, Livio Baldi
  • Patent number: 6747309
    Abstract: A method of manufacturing an integrated semiconductor device having at least one non-volatile floating gate memory cell and at least one logic transistor. The method includes growing a first gate oxide layer over a silicon substrate, depositing a first polysilicon layer over the first gate oxide layer, selectively etching and removing the first polysilicon layer in order to define the floating gate of the memory cell, introducing dopant in order to obtain source and drain regions of the memory cell, depositing a dielectric layer, selectively etching and removing the dielectric layer and the first polysilicon layer in a region wherein the logic transistor will be formed, depositing a second polysilicon layer, selectively etching and removing the second polysilicon layer in order to define the gate of the logic transistor and the control gate of the memory cell.
    Type: Grant
    Filed: April 15, 2002
    Date of Patent: June 8, 2004
    Assignee: STMicroelectronics S.r.l.
    Inventors: Livio Baldi, Maurelli Alfonso
  • Patent number: 6547151
    Abstract: A currency note includes an identification and/or authentication element including an integrated circuit. The integrated circuit can store, securely in electronic form and accessible from outside, such information as: the value, serial number, issuer, and date of issuance.
    Type: Grant
    Filed: August 23, 2000
    Date of Patent: April 15, 2003
    Assignee: STMicroelectronics S.r.l.
    Inventor: Livio Baldi
  • Patent number: 6465950
    Abstract: The microtips of charge emitting material, which define the cathode of the flat FED screen and face the grid of the screen, are tubular and have portions with a small radius of curvature. The microtips are obtained by forming openings in the dielectric layer separating the cathode connection layer from the grid layer, depositing a conducting material layer to cover the walls of the openings, and anisotropically etching the layer of conducting material to form inwardly-inclined surfaces with emitting tips. Subsequently, the portions of the dielectric layer surrounding the microtips are removed.
    Type: Grant
    Filed: January 13, 2000
    Date of Patent: October 15, 2002
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Livio Baldi, Maria Santina Marangon
  • Publication number: 20020119616
    Abstract: A method of manufacturing an integrated semiconductor device having at least one non-volatile floating gate memory cell and at least one logic transistor. The method includes growing a first gate oxide layer over a silicon substrate, depositing a first polysilicon layer over the first gate oxide layer, selectively etching and removing the first polysilicon layer in order to define the floating gate of the memory cell, introducing dopant in order to obtain source and drain regions of the memory cell, depositing a dielectric layer, selectively etching and removing the dielectric layer and the first polysilicon layer in a region wherein the logic transistor will be formed, depositing a second polysilicon layer, selectively etching and removing the second polysilicon layer in order to define the gate of the logic transistor and the control gate of the memory cell.
    Type: Application
    Filed: April 15, 2002
    Publication date: August 29, 2002
    Applicant: STMicroelectronics S.r.I.
    Inventors: Livio Baldi, Alfonso Maurelli