Abstract: The local network comprises a plurality of active nodes (N1 . . . Nn) placed along a folded unidirectional bus (1) which presents a writing branch (1W) and a reading branch (1R). The nodes present means (RR) for network reconfiguration in the presence of a failure, through an isolation of the parts concerned by the failure, through an isolation of the parts concerned by the failure, and for regular service restoration after the repair, and means (GA) for the implementation of an ordered access protocol, which is based on the physical position of the nodes (N1 . . . Nn) and allows hybrid frames to be transmitted through the bus (FIG. 1).

Abstract: The system comprises a plurality of units arranged along a unidirectional line whereupon information is transmitted relevant to circuit switched and packet switched communications and organized into hybrid frames comprising a region for each communication type. The units comprise devices handling the access to the line which cooperate with one another and with a frame signal generator, centralized or associated with each unit, to implement in distributed way an ordered protocol without collisions in both frame region, based on physical unit location.

Abstract: A node in a packet-switching data-transmission network has a processor distributing incoming messages or packets from a receiving buffer to transmitting buffers selected according to routing data established by an updating circuit which algebraically combines incremental delays with respective path delays to obtain total delays assigned to message transmission from the processor over respective transmitting buffers and associated outgoing transmission paths. The increment delays assigned to the respective buffers are calculated by a delay estimator utilizing data from the processor including packet-service times and arrival and departure times of the packets in the various buffers, the path delays assigned to routes extending from the respective transmitting buffers to a terminal node being communicated to the updating circuit via the processor from nodes connected downstream of the transmitting buffers.