Patents by Inventor Liwei Ju

Liwei Ju has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Self-repair logic for stacked memory architecture
    Patent number: 10224115
    Abstract: Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a first memory die element, and a system element coupled with the memory stack. The first memory die element includes multiple through silicon vias (TSVs), the TSVs including data TSVs and one or more spare TSVs, and self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: March 5, 2019
    Assignee: Intel Corporation
    Inventors: Joon-Sung Yang, Darshan Kobla, Liwei Ju, David Zimmerman
  • SELF-REPAIR LOGIC FOR STACKED MEMORY ARCHITECTURE
    Publication number: 20180005709
    Abstract: Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a first memory die element, and a system element coupled with the memory stack. The first memory die element includes multiple through silicon vias (TSVs), the TSVs including data TSVs and one or more spare TSVs, and self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs.
    Type: Application
    Filed: May 8, 2017
    Publication date: January 4, 2018
    Applicant: Intel Corporation
    Inventors: Joon-Sung YANG, Darshan KOBLA, Liwei JU, David ZIMMERMAN
  • Self-repair logic for stacked memory architecture
    Patent number: 9646720
    Abstract: Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a first memory die element, and a system element coupled with the memory stack. The first memory die element includes multiple through silicon vias (TSVs), the TSVs including data TSVs and one or more spare TSVs, and self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: May 9, 2017
    Assignee: Intel Corporation
    Inventors: Joon-Sung Yang, Darshan Kobla, Liwei Ju, David Zimmerman
  • SELF-REPAIR LOGIC FOR STACKED MEMORY ARCHITECTURE
    Publication number: 20160055922
    Abstract: Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a first memory die element, and a system element coupled with the memory stack. The first memory die element includes multiple through silicon vias (TSVs), the TSVs including data TSVs and one or more spare TSVs, and self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs.
    Type: Application
    Filed: July 29, 2015
    Publication date: February 25, 2016
    Inventors: Joon-Sung Yang, Darshan Kobla, Liwei Ju, David Zimmerman
  • Self-repair logic for stacked memory architecture
    Patent number: 9136021
    Abstract: Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a first memory die element, and a system element coupled with the memory stack. The first memory die element includes multiple through silicon vias (TSVs), the TSVs including data TSVs and one or more spare TSVs, and self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: September 15, 2015
    Assignee: Intel Corporation
    Inventors: Joon-Sung Yang, Darshan Kobla, Liwei Ju, David Zimmerman
  • SELF-REPAIR LOGIC FOR STACKED MEMORY ARCHITECTURE
    Publication number: 20130294184
    Abstract: Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a first memory die element, and a system element coupled with the memory stack. The first memory die element includes multiple through silicon vias (TSVs), the TSVs including data TSVs and one or more spare TSVs, and self-repair logic to repair operation of a defective TSV of the plurality of data TSVs, the repair of operation of the defective TSV including utilization of the one or more spare TSVs.
    Type: Application
    Filed: December 23, 2011
    Publication date: November 7, 2013
    Inventors: Joon-Sung Yang, Darshan Kobla, Liwei Ju, David Zimmerman