Abstract: A method includes forming an n-type Fin-Field Effect Transistor (FinFET) and a p-type FinFET. The forming of the n-type FinFFT includes: forming a first auxiliary gate stack over a first semiconductor fin; forming an n-type source/drain region on the first semiconductor fin adjacent to the first auxiliary gate stack; and performing a first etch to form a first recess with a first depth on a first top surface of the n-type source/drain region. The forming of the p-type FinFFT includes: forming a second auxiliary gate stack over a second semiconductor fin; forming a p-type source/drain region on the second semiconductor fin adjacent to the second auxiliary gate stack; and performing a second etch to form a second recess with a second depth on a second top surface of the p-type source/drain region. The first depth is greater than the second depth.

Abstract: A source driving circuit of a display includes a gamma resistor strings, a digital to analog (DAC) circuit, and an output buffer circuit. The output buffer circuit includes input stage module, gain stage module, and output stage module. The input stage module includes main input stage unit and auxiliary input stage unit. Sizes of elements in main input stage unit are larger than sizes of elements in the auxiliary input stage unit, smaller sizes presenting smaller parasitic capacitances. During the switching period, the auxiliary input stage unit, gain stage module, and output stage module form a first unity gain amplifier outputting the driving voltages. During the stable period, the main input stage unit, gain stage module, and output stage module form a second unity gain amplifier outputting the driving voltages. A display device is also disclosed.

Abstract: A flash includes a substrate comprising an active region and two electron storage structures disposed at two sides of the active region, wherein each of the electron storage structures comprises a silicon oxide/silicon nitride/silicon oxide composite layer. A buried gate is embedded in the active region, wherein the buried gate only consists of a control gate and a gate dielectric layer, and the gate dielectric layer is formed by a single material. Two source/drain doping regions are disposed in the active region at two sides of the buried gate.

Abstract: A light-emitting diode package includes a substrate, at least one light-emitting chip, a light-reflective layer and a wave-length conversion fluorescent layer. The light-emitting chip is located on the substrate. The light-reflective layer is arranged around the light-emitting chip. The wave-length conversion fluorescent layer is located over the light-emitting chip, wherein the light-reflective layer is spaced from the fluorescent wave-length conversion layer by a groove that reaches two opposite sides of the light-emitting diode package.

Abstract: A flash includes a substrate comprising an active region and two electron storage structures disposed at two sides of the active region, wherein each of the electron storage structures comprises a silicon oxide/silicon nitride/silicon oxide composite layer. A buried gate is embedded in the active region, wherein the buried gate only consists of a control gate and a gate dielectric layer, and the gate dielectric layer is formed by a single material. Two source/drain doping regions are disposed in the active region at two sides of the buried gate.

Abstract: A light-emitting diode package includes a substrate, at least one light-emitting chip, a light-reflective layer and a wave-length conversion fluorescent layer. The light-emitting chip is located on the substrate. The light-reflective layer is arranged around the light-emitting chip. The wave-length conversion fluorescent layer is located over the light-emitting chip, wherein the light-reflective layer is spaced from the fluorescent wave-length conversion layer by a groove that reaches two opposite sides of the light-emitting diode package.

Abstract: A manufacturing method of a semiconductor memory device includes following steps. Bit line structures and storage node contacts are formed on a semiconductor substrate. A first sidewall spacer is formed on sidewalls of each bit line structure. A conductive layer covering the bit line structures, the first sidewall spacer, and the storage node contacts is formed. A first patterning process is preformed to the conductive layer for forming stripe contact structures. Each stripe contact structure is elongated in the first direction and corresponding to the storage node contacts. The first sidewall spacer at a first side of each bit line structure is exposed by the first patterning process. The first sidewall spacer at a second side of each bit line structure is covered by the stripe contact structures. The first sidewall spacer exposed by the first patterning process is removed for forming first air spacers.

Abstract: A manufacturing method of a casing is provided. First, a plate, a frame and a main shell are provided, wherein the plate has an adhering region and at least one thermal fusion region, and the frame has a first surface and a second surface opposite to each other. Then, the plate is stacked on the first surface of the frame, wherein the thermal fusion region is overlapped with the frame, and the adhering region is not overlapped with the frame. The main shell is adhered to the adhering region of the plate and the second surface of the frame. The thermal fusion region is fixed to the frame by thermal fusion. In addition, a casing manufactured through the above-mentioned method is also provided.

Abstract: A manufacturing method of a semiconductor memory device includes following steps. Bit line structures and storage node contacts are formed on a semiconductor substrate. A first sidewall spacer is formed on sidewalls of each bit line structure. A conductive layer covering the bit line structures, the first sidewall spacer, and the storage node contacts is formed. A first patterning process is preformed to the conductive layer for forming stripe contact structures. Each stripe contact structure is elongated in the first direction and corresponding to the storage node contacts. The first sidewall spacer at a first side of each bit line structure is exposed by the first patterning process. The first sidewall spacer at a second side of each bit line structure is covered by the stripe contact structures. The first sidewall spacer exposed by the first patterning process is removed for forming first air spacers.

Abstract: A manufacturing method of a semiconductor memory device includes following steps. Bit line structures and storage node contacts are formed on a semiconductor substrate. A first sidewall spacer is formed on sidewalls of each bit line structure. A conductive layer covering the bit line structures, the first sidewall spacer, and the storage node contacts is formed. A first patterning process is preformed to the conductive layer for forming stripe contact structures. Each stripe contact structure is elongated in the first direction and corresponding to the storage node contacts. The first sidewall spacer at a first side of each bit line structure is exposed by the first patterning process. The first sidewall spacer at a second side of each bit line structure is covered by the stripe contact structures. The first sidewall spacer exposed by the first patterning process is removed for forming first air spacers.

Abstract: A manufacturing method of a semiconductor memory device includes following steps. Bit line structures and storage node contacts are formed on a semiconductor substrate. A first sidewall spacer is formed on sidewalls of each bit line structure. A conductive layer covering the bit line structures, the first sidewall spacer, and the storage node contacts is formed. A first patterning process is preformed to the conductive layer for forming stripe contact structures. Each stripe contact structure is elongated in the first direction and corresponding to the storage node contacts. The first sidewall spacer at a first side of each bit line structure is exposed by the first patterning process. The first sidewall spacer at a second side of each bit line structure is covered by the stripe contact structures. The first sidewall spacer exposed by the first patterning process is removed for forming first air spacers.

Abstract: A pixel circuit includes a first capacitor, an input unit, a driving unit, a first compensation unit, an organic light-emitting diode, a switch unit, a second compensation unit and a reset unit. The input unit is electrically connected to the first capacitor and the second compensation unit. The second compensation unit is electrically connected to the organic light-emitting diode. The first compensation unit is electrically connected to the first capacitor, the driving unit, the switch unit and the reset unit. The driving unit is electrically connected to the switch unit and the reset unit. The switch unit is electrically connected to the organic light-emitting diode. The pixel circuit is configured to generate a corresponding driving current according to a turn-on voltage of the organic light-emitting diode. A driving method of a pixel circuit is also provided.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a trench in a substrate; performing an ion implantation process to implant ions into the substrate underneath the trench; performing an in-situ steam generation (ISSG) process to form a gate dielectric layer in the trench; forming a gate electrode on the gate dielectric layer; and forming a doped region in the substrate adjacent to two sides of the gate electrode.

Abstract: A display apparatus includes a display unit, a source driver, a gate driver and a compensation unit. The display unit includes at least a pixel unit. Each pixel unit includes a first transistor, a second transistor, a first capacitor, a second capacitor and an organic light emitting diode. When the pixel unit is operated in a display mode, the pixel unit outputs a sensing voltage including a first parameter having characteristics of the second transistor and a second parameter having characteristics of the organic light emitting diode. The source driver receives a compensation data and accordingly adjusts the next display data. The compensation unit is disposed between the second capacitor and the source driver and electrically coupled between the second end of the second capacitor and the source driver. The compensation unit receives the sensing voltage and outputs the compensation data according to the received sensing voltage.

Abstract: A pixel circuit includes a first capacitor, an input unit, a driving unit, a first compensation unit, an organic light-emitting diode, a switch unit, a second compensation unit and a reset unit. The input unit is electrically connected to the first capacitor and the second compensation unit. The second compensation unit is electrically connected to the organic light-emitting diode. The first compensation unit is electrically connected to the first capacitor, the driving unit, the switch unit and the reset unit. The driving unit is electrically connected to the switch unit and the reset unit. The switch unit is electrically connected to the organic light-emitting diode. The pixel circuit is configured to generate a corresponding driving current according to a turn-on voltage of the organic light-emitting diode. A driving method of a pixel circuit is also provided.

Abstract: An electrical deposition apparatus includes a brush plating head. The brush plating head includes a plurality of channels, and there are openings at the same surface of the brush plating head. Each of the channels extends from within the brush plating head to each of the openings.

Abstract: A manufacturing method of a casing is provided. First, a plate, a frame and a main shell are provided, wherein the plate has an adhering region and at least one thermal fusion region, and the frame has a first surface and a second surface opposite to each other. Then, the plate is stacked on the first surface of the frame, wherein the thermal fusion region is overlapped with the frame, and the adhering region is not overlapped with the frame. The main shell is adhered to the adhering region of the plate and the second surface of the frame. The thermal fusion region is fixed to the frame by thermal fusion. In addition, a casing manufactured through the above-mentioned method is also provided.

Abstract: A pixel driving circuit includes a light emitting diode (LED), a data writing unit, two transistors and two compensation units. The gate of the first transistor is coupled to the data writing unit for determining the current flow of the LED. The first compensation unit is coupled to the first transistor for providing a current path from the gate of the first transistor to a first voltage source and a current path from the gate of the first transistor to a second voltage source. The second compensation unit includes a first capacitor coupled to the gate of the first transistor for voltage coupling and providing a differential voltage that equals to the OLED to the gate of the first transistor. The second transistor is coupled between the first voltage source and a second voltage source for enabling or disabling the current flow between the first and second voltage sources.

Abstract: A manufacturing method of a casing is provided. First, a plate, a frame and a main shell are provided, wherein the plate has an adhering region and at least one thermal fusion region, and the frame has a first surface and a second surface opposite to each other. Then, the plate is stacked on the first surface of the frame, wherein the thermal fusion region is overlapped with the frame, and the adhering region is not overlapped with the frame. The main shell is adhered to the adhering region of the plate and the second surface of the frame. The thermal fusion region is fixed to the frame by thermal fusion. In addition, a casing manufactured through the above-mentioned method is also provided.

Abstract: A light emitting diode module includes a light emitting unit and a light emitting diode circuit. The light emitting diode circuit includes four transistors and a storage capacitor. A first transistor includes a first end for receiving a data signal, and a control end. The storage capacitor has a first end coupled to a second end of the first transistor. A second transistor has a first end coupled to a first voltage source, and a control end. A third transistor has a first end coupled to a second end of the second transistor, and a control end coupled to a second end of the storage capacitor. A fourth transistor has a first end coupled to the second end of the storage capacitor, a control end, and a second end coupled to the second end of the second transistor.