Abstract: A wafer level packaging structure of a high-pixel image sensor chip comprises an image sensor chip, a supporting substrate and a light-transmitting substrate, the image sensor chip comprises a base, a sensing region formed on a first surface of the base; the supporting substrate is attached to the first surface of the base and provided with a first opening penetrating through the supporting substrate at a position corresponding to the sensing region, and the sensing region is exposed from a bottom of the first opening; and the light-transmitting substrate is fixed on a first surface plane of the supporting substrate and covers a top of the first opening, and two surface planes of the light-transmitting substrate are parallel with a plane on which the sensing region is located.

Abstract: One embodiment of the present invention provides a device for providing a low noise power supply package to an IC in the mid-frequency range of 1 MHz to 3 GHz including installing in said package an array of embedded discrete ceramic capacitors, and optionally planar capacitor layers. A further embodiment provides a device for providing a low noise power supply package to an IC in the mid-frequency range of 1 MHz to 3 GHz including an array of embedded discrete ceramic capacitors with different resonance frequencies, arranged in such a way that the capacitor array's impedance vs frequency curve in the critical mid-frequency range yields impedance values at or below a targeted impedance value.

Abstract: The present invention discloses capacitors having via connections and electrodes designed such that they provide a low inductance path, thus reducing needed capacitance, while enabling the use of embedded capacitors for power delivery and other uses. One embodiment of the present invention discloses a capacitor comprising the following: a top capacitor electrode and a bottom capacitor electrode, wherein the top electrode is smaller than the bottom electrode, comprising, on all sides of the capacitor; in an array, a multiplicity of vias located on all sides of the top and bottom capacitor electrodes, wherein the top electrode and the vias connecting to the top electrode act as an inner conductor, and the bottom electrode and the vias connecting to the bottom electrode act as an outer conductor.

Abstract: One embodiment of the present invention provides a device for providing a low noise power supply package to an IC in the mid-frequency range of 1 MHz to 3 GHz comprising installing in said package an array of embedded discrete ceramic capacitors, and optionally planar capacitor layers. A further embodiment provides a device for providing a low noise power supply package to an IC in the mid-frequency range of 1 MHz to 3 GHz comprising using an array of embedded discrete ceramic capacitors with different resonance frequencies, arranged in such a way that the capacitor array's impedance vs frequency curve in the critical mid-frequency range yields impedance values at or below a targeted impedance value.

Abstract: The present invention discloses capacitors having via connections and electrodes designed such that they provide a low inductance path, thus reducing needed capacitance, while enabling the use of embedded capacitors for power delivery and other uses. One embodiment of the present invention discloses a capacitor comprising the following: a top capacitor electrode and a bottom capacitor electrode, wherein the top electrode is smaller than the bottom electrode, comprising, on all sides of the capacitor; in an array, a multiplicity of vias located on all sides of the top and bottom capacitor electrodes, wherein the top electrode and the vias connecting to the top electrode act as an inner conductor, and the bottom electrode and the vias connecting to the bottom electrode act as an outer conductor.