Abstract: Disclosed are examples of a device and method of fabricating a device including a first top contact, a second top contact, adjacent the first top contact, a first mesa disposed below the first top contact and a second mesa disposed below the second top contact. A first plate of a metal-insulator-metal (MIM) capacitor is disposed below the first top contact and electrically coupled to the first top contact. A first insulator of the MIM capacitor is disposed on the first plate. A second plate of the MIM capacitor is disposed on the first insulator and electrically coupled to the second top contact. A second insulator of the MIM capacitor is disposed on the second plate. A third plate of the MIM capacitor is disposed on the second insulator and electrically coupled to the first top contact.

Abstract: Disclosed are examples of a device and method of fabricating a device including a first top contact, a second top contact, adjacent the first top contact, a first mesa disposed below the first top contact and a second mesa disposed below the second top contact. A first plate of a metal-insulator-metal (MIM) capacitor is disposed below the first top contact and electrically coupled to the first top contact. A first insulator of the MIM capacitor is disposed on the first plate. A second plate of the MIM capacitor is disposed on the first insulator and electrically coupled to the second top contact. A second insulator of the MIM capacitor is disposed on the second plate. A third plate of the MIM capacitor is disposed on the second insulator and electrically coupled to the first top contact.

Abstract: 3D vertically-integrated FETs electrically coupled by integrated vertical FET-to-FET interconnects for reducing an area of CMOS cell circuits are disclosed. Vertically integrated FETs reduce a footprint area of an integrated circuit chip. The FETs include horizontal channel structures that are vertically integrated by stacking a second channel structure of a second FET above a first channel structure of a first FET. The first and second FETs can include a combination of a PFET and NFET that can be used to form a 3D CMOS cell circuit as an example. The area occupied by the 3D CMOS cell circuit includes interconnects for electrically coupling terminal regions of the FETs internally and externally. Vertical FET-to-FET interconnects extend between the FETs to electrically couple terminal regions of the FETs to reduce a number of vias from a semiconductor layer of the 3D CMOS cell circuit to metal interconnect layers above the vertically-integrated FETs.

Abstract: Certain aspects of the present disclosure generally relate to a hybrid back-end-of-line (BEOL) dielectric for a high capacitance density metal-oxide-metal (MOM) capacitor, especially in lower BEOL layers. One example semiconductor device includes an active layer and a first metal layer disposed above the active layer. The first metal layer generally includes: a first electrode; a second electrode, wherein the first and second electrodes have interdigitated fingers; a first dielectric material disposed at least partially between at least two adjacent fingers of the first and second electrodes; and a second dielectric material, wherein the second dielectric material is different from the first dielectric material and wherein the first electrode, the second electrode, and the first dielectric material compose a portion of a metal-oxide-metal (MOM) capacitor.

Abstract: Certain aspects of the present disclosure generally relate to transistors in a layered arrangement. An example semiconductor device generally includes a substrate, an n-type metal-oxide-semiconductor (NMOS) transistor, and a p-type metal-oxide-semiconductor (PMOS) transistor. The NMOS transistor is disposed above the substrate and is a gate-all-around (GAA) field-effect transistor (FET). The PMOS transistor is disposed above the substrate, is a fin field-effect transistor (finFET), and is in a layered arrangement with the NMOS transistor.

Abstract: 3D vertically-integrated FETs electrically coupled by integrated vertical FET-to-FET interconnects for reducing an area of CMOS cell circuits are disclosed. Vertically integrated FETs reduce a footprint area of an integrated circuit chip. The FETs include horizontal channel structures that are vertically integrated by stacking a second channel structure of a second FET above a first channel structure of a first FET. The first and second FETs can include a combination of a PFET and NFET that can be used to form a 3D CMOS cell circuit as an example. The area occupied by the 3D CMOS cell circuit includes interconnects for electrically coupling terminal regions of the FETs internally and externally. Vertical FET-to-FET interconnects extend between the FETs to electrically couple terminal regions of the FETs to reduce a number of vias from a semiconductor layer of the 3D CMOS cell circuit to metal interconnect layers above the vertically-integrated FETs.

Abstract: Methods and apparatuses for different types of non-planar transistors within a stack are presented. The apparatus includes a p-type transistor and an n-type transistor arranged in a stack vertically above a substrate, the p-type transistor and the n-type transistor being non-planar transistors. The p-type transistor includes a p-type channel and a first set of work function layer. The first set of work function layer surrounds the p-type channel. The p-type channel is configured for p-type conductivity based on the first set of work function layer. The n-type transistor includes an n-type channel and a second set of work function layer. The second set of work function layer surrounds the n-type channel. The n-type channel is configured for n-type conductivity based on the second set of work function layer. The first set of work function layer and the second set of work function layer are different.

Abstract: An integrated circuit may include a substrate, a first three-dimensional (3D) transistor formed on a first diffusion region of the substrate, and a second 3D transistor formed on a second diffusion region of the substrate. The first 3D transistor may include a gate that extends from between a source and a drain of the first 3D transistor, across an isolation region of the substrate, to and between a source and a drain of the second 3D transistor. The gate may include a gate metal that has an isolation portion extending over the isolation region of the substrate and a diffusion portion extending over the first and second diffusion regions of the substrate. The isolation portion of the gate metal has a thickness less than a maximum thickness of the diffusion portion of the gate metal.

Abstract: A Field-Effect Transistor (FET) with a negative capacitance layer to increase power density provides a negative capacitor connected in series with a conventional positive capacitor. The dimensions of the negative capacitor are controlled to allow the difference in capacitances between the negative capacitor and the positive capacitor to approach zero, which in turn provides a large total capacitance. The large total capacitance provides for increased power density.

Abstract: An integrated circuit (IC) device may include a semiconductor structure. The semiconductor structure may include a source contact, a drain contact, and a gate. A first fluorocarbon spacer may be between the gate and the source contact. A second fluorocarbon spacer may be between the gate and the drain contact.

Abstract: A complementary metal-oxide-semiconductor (CMOS) transistor may include a first semiconductor structure and a gate stack on the first semiconductor structure. The gate stack may include a gate dielectric layer on the first semiconductor structure, a work function material on the gate dielectric layer, and a gate metal fill material on the work function material of the gate stack. The gate metal fill material may include a low resistivity carbon alloy. A dielectric fill material may be included on the gate stack.

Abstract: Certain aspects of the present disclosure provide a memory implemented using negative capacitance material. One example memory generally includes a transistor coupled to a word-line of the memory and a bit-line of the memory, and a capacitive element coupled to the transistor. The capacitive element may include a first layer of dielectric material and a second layer of negative capacitance material, the first layer and the second layer being between a first non-insulative region coupled to the transistor and a second non-insulative region.

Abstract: A Field-Effect Transistor (FET) with a negative capacitance layer to increase power density provides a negative capacitor connected in series with a conventional positive capacitor. The dimensions of the negative capacitor are controlled to allow the difference in capacitances between the negative capacitor and the positive capacitor to approach zero, which in turn provides a large total capacitance. The large total capacitance provides for increased power density.

Abstract: An integrated circuit (IC) device may include a semiconductor structure. The semiconductor structure may include a source contact, a drain contact, and a gate. A first fluorocarbon spacer may be between the gate and the source contact. A second fluorocarbon spacer may be between the gate and the drain contact.

Abstract: Middle-of-line (MOL) metal resistor temperature sensors for localized temperature sensing of active semiconductor areas in integrated circuits (ICs) are disclosed. One or more metal resistors are fabricated in a MOL layer in the IC adjacent to an active semiconductor area to sense ambient temperature in the adjacent active semiconductor area. Voltage of the metal resistor will change as a function of ambient temperature of the metal resistor, which can be sensed to measure the ambient temperature around devices in the active semiconductor layer adjacent to the metal resistor. By fabricating a metal resistor in the MOL layer, the metal resistor can be localized adjacent and close to semiconductor devices to more accurately sense ambient temperature of the semiconductor devices. The same fabrication processes used to create contacts in the MOL layer can be used to fabricate the metal resistor.

Abstract: A short-channel metal oxide semiconductor varactor may include a source region of a first polarity having a source via contact. The varactor may further include a drain region of the first polarity having a drain via contact. The varactor may further include a channel region of the first polarity between the source region and the drain region. The channel region may include a gate. The varactor may further include at least one self-aligned contact (SAC) on the gate and between the source via contact and the drain via contact.

Abstract: An integrated circuit may include a substrate, a first three-dimensional (3D) transistor formed on a first diffusion region of the substrate, and a second 3D transistor formed on a second diffusion region of the substrate. The first 3D transistor may include a gate that extends from between a source and a drain of the first 3D transistor, across an isolation region of the substrate, to and between a source and a drain of the second 3D transistor. The gate may include a gate metal that has an isolation portion extending over the isolation region of the substrate and a diffusion portion extending over the first and second diffusion regions of the substrate. The isolation portion of the gate metal has a thickness less than a maximum thickness of the diffusion portion of the gate metal.

Abstract: An integrated circuit (IC) device may include a semiconductor structure. The semiconductor structure may include a source contact, a drain contact, and a gate. A first fluorocarbon spacer may be between the gate and the source contact. A second fluorocarbon spacer may be between the gate and the drain contact.

Abstract: Middle-of-line (MOL) shielded gate in integrated circuits (ICs) are disclosed. One or more metal resistors are fabricated in a MOL layer in the IC to reduce gate to drain parasitic capacitance in the semiconductor area. By fabricating a metal resistor in the MOL layer, the metal resistor can be localized close to semiconductor devices to more effectively reduce parasitic capacitance of the semiconductor devices without adding costs or defects to the current fabrication processes. The current fabrication processes may be used to create contacts in the MOL to fabricate the metal resistor.

Abstract: Middle-of-line (MOL) metal resistor temperature sensors for localized temperature sensing of active semiconductor areas in integrated circuits (ICs) are disclosed. One or more metal resistors are fabricated in a MOL layer in the IC adjacent to an active semiconductor area to sense ambient temperature in the adjacent active semiconductor area. Voltage of the metal resistor will change as a function of ambient temperature of the metal resistor, which can be sensed to measure the ambient temperature around devices in the active semiconductor layer adjacent to the metal resistor. By fabricating a metal resistor in the MOL layer, the metal resistor can be localized adjacent and close to semiconductor devices to more accurately sense ambient temperature of the semiconductor devices. The same fabrication processes used to create contacts in the MOL layer can be used to fabricate the metal resistor.