Abstract: A resistive random access memory array and an operation method therefor, and a resistive random access memory circuit. The resistive random access memory array includes multiple memory cells, multiple bit lines, multiple word lines, multiple block selection circuits, and multiple initialization circuits. Each memory cell includes a resistive random access memory device and a switching device. The multiple memory cells are arranged into multiple memory cell rows and multiple memory cell columns in a first direction and a second direction, and the multiple bit lines and the multiple memory cell columns are connected in one-to-one correspondence. Each block selection circuit is configured to write a read/write operation voltage into a correspondingly connected bit line in response to a block selection voltage. Each initialization circuit is configured to write an initialization operation voltage to a correspondingly connected bit line in response to an initialization control voltage.

Abstract: The random access memory includes: two identical memory cell arrays, a data write circuit and a data read circuit. Array structures of the two identical memory cell arrays are the same, and same original stored information is stored in memory cells with a same address in the two identical memory cell arrays. The data write circuit is configured to write same data into the memory cells with the same address in the two identical memory cell arrays. The data read circuit is configured to select two pieces of stored information from the memory cells with the same address in the two identical memory cell arrays, and to output “0” if the two pieces of stored information are different or output one of the two pieces of stored information if the two pieces of stored information are the same.

Abstract: The present disclosure provides a cell structure, a random access memory and operation methods. The cell structure with four transistors, including a first N-type transistor, a first P-type transistor, a second N-type transistor and a second P-type transistor, in which an absolute value of a threshold voltage of the first N-type transistor is greater than an absolute value of a threshold voltage of the second N-type transistor, and an absolute value of a threshold voltage of the first P-type transistor is greater than an absolute value of a threshold voltage of the second P-type transistor. The random access memory, including: two identical memory cell arrays including the cell structure with four transistors, a data write circuit and a data read circuit, by using Two Modular Redundancy harden method, and thus reading correctly and avoiding the mistake reversal caused by the single event upset effect.

Abstract: The present disclosure provides a random access memory. The random access memory includes: two identical memory cell arrays, a data write circuit and a data read circuit. Array structures of the two identical memory cell arrays are same, and same original stored information is stored in memory cells with a same address in the two identical memory cell arrays. The data write circuit is configured to write same data into the memory cells with the same address in the two identical memory cell arrays. The data read circuit is configured to select two pieces of stored information from the memory cells with the same address in the two identical memory cell arrays, and to output “0” if the two pieces of stored information are different or output one of the two pieces of stored information if the two pieces of stored information are same.

Abstract: The present invention discloses a wear leveling method; the method determines a pool mask for each physical block based on an erase number of each physical block. For different erase numbers, masks of the physical blocks are determined as cool pool mask CPM, normal pool mask NPM or hot pool mask HPM. When the pool mask of one physical block is changed from NPM to HPM, data of any physical block of which the pool mask is CPM is copied to the physical block of which the pool mask is HPM, and the physical block of which the pool mask is CPM is recycled as a garbage block. The present invention discloses a wear leveling apparatus, the method and apparatus can reduce additional wear caused by the wear leveling.

Abstract: The present disclosure provides a cell structure, a random access memory and operation methods. The cell structure with four transistors, including a first N-type transistor, a first P-type transistor, a second N-type transistor and a second P-type transistor, in which an absolute value of a threshold voltage of the first N-type transistor is greater than an absolute value of a threshold voltage of the second N-type transistor, and an absolute value of a threshold voltage of the first P-type transistor is greater than an absolute value of a threshold voltage of the second P-type transistor. The random access memory, including: two identical memory cell arrays including the cell structure with four transistors, a data write circuit and a data read circuit, by using Two Modular Redundancy harden method, and thus reading correctly and avoiding the mistake reversal caused by the single event upset effect.

Abstract: A vertically foldable memory array structure is provided, comprising: a memory module distributed in columns and rows, comprising: a drain selection transistor; a bottom connecting line and a source selection transistor; and a plurality of memory cell transistors connected between the drain selection transistor and the bottom connecting line and between the source selection transistor and the bottom connecting line, a drain of each drain selection transistor is connected to a bit line, a drain of a drain selection transistor in a Mth vertically foldable memory module in a Nth column and a source of a source selection transistor in a (M?1)th memory module in a (N+1)th column are connected to a same bit line, gates of the drain selection transistors and the source selection transistors in all the memory modules in the Nth column are connected to a same drain selection line and a same source selection line.

Abstract: A NOR flash memory array structure is provided, comprising: a substrate (100); and a two dimensional memory array structure formed on the substrate (100) and comprising: a plurality of memory cell columns arranged in a first direction, and each memory cell column including a plurality of memory cells (300), in which each memory cell (300) comprises: a channel region (308) located on the substrate (100), a gate structure located on the channel region (308) and formed by a tunneling oxide layer (304), a silicon nitride layer (303), a barrier oxide layer (302) and a polysilicon gate layer (301) stacked sequentially, a source region (306) and a drain region (305) located at a first edge and a second edge of the gate structure respectively; a plurality of word lines WL; a source line SL for connecting the source regions of all the memory cells; and a plurality of bit lines BL.

Abstract: The present disclosure discloses a vertical selection transistor, a memory cell having the vertical selection transistor, a three-dimensional memory array structure and a method for fabricating the three-dimensional memory array structure. The vertical selection transistor comprises: an upper electrode; a lower electrode; a first semiconductor layer, a second semiconductor layer, a third semiconductor layer and a fourth semiconductor layer vertically stacked between the lower electrode and the upper electrode; and a gate stack formed on a side of the second semiconductor layer, in which the first semiconductor layer and the third semiconductor layer are first type doped layers, the second semiconductor layer and the fourth semiconductor layer are second type doped layers, and a doping concentration of the second semiconductor layer is lower than that of the first semiconductor layer or that of the third semiconductor layer respectively.

Abstract: A NOR flash memory array structure is provided, comprising: a substrate (100); and a two dimensional memory array structure formed on the substrate (100) and comprising: a plurality of memory cell columns arranged in a first direction, and each memory cell column including a plurality of memory cells (300), in which each memory cell (300) comprises: a channel region (308) located on the substrate (100), a gate structure located on the channel region (308) and formed by a tunneling oxide layer (304), a silicon nitride layer (303), a barrier oxide layer (302) and a polysilicon gate layer (301) stacked sequentially, a source region (306) and a drain region (305) located at a first edge and a second edge of the gate structure respectively; a plurality of word lines WL; a source line SL for connecting the source regions of all the memory cells; and a plurality of bit lines BL.

Abstract: A memory array structure and a method for forming the same are provided. The memory array structure comprises: a substrate; a plurality of memory cells, each memory cell including a vertical transistor, of which a gate structure is formed in a first trench extending in a first direction; a plurality of word lines in the first direction, each word line formed in the first trench; a plurality of bit lines in a second direction, each bit line formed in lower sides of a semiconductor pillars; a plurality of body lines in the first direction, each body line having a first portion formed on the gate electrodes and a second portion covering a part of a top surface of semiconductor pillar for providing a substrate contact to vertical channel regions; and a plurality of data storage device contacts.

Abstract: The present disclosure discloses a vertical selection transistor, a memory cell having the vertical selection transistor, a three-dimensional memory array structure and a method for fabricating the three-dimensional memory array structure. The vertical selection transistor comprises: an upper electrode; a lower electrode; a first semiconductor layer, a second semiconductor layer, a third semiconductor layer and a fourth semiconductor layer vertically stacked between the lower electrode and the upper electrode; and a gate stack formed on a side of the second semiconductor layer, in which the first semiconductor layer and the third semiconductor layer are first type doped layers, the second semiconductor layer and the fourth semiconductor layer are second type doped layers, and a doping concentration of the second semiconductor layer is lower than that of the first semiconductor layer or that of the third semiconductor layer respectively.

Abstract: A memory array structure and a method for forming the same are provided. The memory array structure comprises: a substrate; a plurality of memory cells, each memory cell including a vertical transistor, of which a gate structure is formed in a first trench extending in a first direction; a plurality of word lines in the first direction, each word line formed in the first trench; a plurality of bit lines in a second direction, each bit line formed in lower sides of a semiconductor pillars; a plurality of body lines in the first direction, each body line having a first portion formed on the gate electrodes and a second portion covering a part of a top surface of semiconductor pillar for providing a substrate contact to vertical channel regions; and a plurality of data storage device contacts.

Abstract: A vertically foldable memory array structure is provided, comprising: a memory module distributed in columns and rows, comprising: a drain selection transistor; a bottom connecting line and a source selection transistor; and a plurality of memory cell transistors connected between the drain selection transistor and the bottom connecting line and between the source selection transistor and the bottom connecting line, a drain of each drain selection transistor is connected to a bit line, a drain of a drain selection transistor in a Mth vertically foldable memory module in a Nth column and a source of a source selection transistor in a (M?1)th memory module in a (N+1)th column are connected to a same bit line, gates of the drain selection transistors and the source selection transistors in all the memory modules in the Nth column are connected to a same drain selection line and a same source selection line.

Abstract: The present invention discloses a wear leveling method; the method determines a pool mask for each physical block based on an erase number of each physical block. For different erase numbers, masks of the physical blocks are determined as cool pool mask CPM, normal pool mask NPM or hot pool mask HPM. When the pool mask of one physical block is changed from NPM to HPM, data of any physical block of which the pool mask is CPM is copied to the physical block of which the pool mask is HPM, and the physical block of which the pool mask is CPM is recycled as a garbage block. The present invention discloses a wear leveling apparatus, the method and apparatus can reduce additional wear caused by the wear leveling.