Patents by Inventor Liyang Song
Liyang Song has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10817779Abstract: Data includes data with labels and data without labels. For data without labels a fuzzy rules system assigns pseudo labels. A computer processes the data with labels using a first cognitive neural network; processes the data with pseudo labels using a second cognitive neural network; and produces system outcomes by combining the results of the first and second cognitive neural networks. The computer obtains feedback on the system outcomes, and modifies parameters of the fuzzy rule system in response to the feedback.Type: GrantFiled: August 30, 2017Date of Patent: October 27, 2020Assignee: International Business Machines CorporationInventors: Elizabeth Bourgoin, Christopher A. Buchholz, Eric M. Kessler, Liyang Song, Zhihuai Zhu
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Patent number: 10256150Abstract: A method is presented for creating an asymmetrical split-gate structure. The method includes forming a first device, forming a second device, forming a first gate stack between a first set of spacers of the first device, and a second gate stack between a second set of spacers of the second device. The method further includes depositing a hard mask over the first and second gate stacks, etching a first section of the first gate stack to create a first gap and a second section of the second gate stack to create a second gap, and forming a third gate stack within the first gap of the first gate stack and within the second gap of the second gate stack such that dual gate stacks are defined for each of the first and second devices. The method further includes annealing the dual gate stacks to form replacement metal gate stacks.Type: GrantFiled: April 3, 2017Date of Patent: April 9, 2019Assignee: International Business Machines CorporationInventors: Dechao Guo, Liyang Song, Xinhui Wang, Qintao Zhang
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Publication number: 20190065939Abstract: Data includes data with labels and data without labels. For data without labels a fuzzy rules system assigns pseudo labels. A computer processes the data with labels using a first cognitive neural network; processes the data with pseudo labels using a second cognitive neural network; and produces system outcomes by combining the results of the first and second cognitive neural networks. The computer obtains feedback on the system outcomes, and modifies parameters of the fuzzy rule system in response to the feedback.Type: ApplicationFiled: August 30, 2017Publication date: February 28, 2019Inventors: Elizabeth Bourgoin, Christopher A. Buchholz, Eric M. Kessler, Liyang Song, Zhihuai Zhu
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Patent number: 10170368Abstract: A method is presented for creating an asymmetrical split-gate structure. The method includes forming a first device, forming a second device, forming a first gate stack between a first set of spacers of the first device, and a second gate stack between a second set of spacers of the second device. The method further includes depositing a hard mask over the first and second gate stacks, etching a first section of the first gate stack to create a first gap and a second section of the second gate stack to create a second gap, and forming a third gate stack within the first gap of the first gate stack and within the second gap of the second gate stack such that dual gate stacks are defined for each of the first and second devices. The method further includes annealing the dual gate stacks to form replacement metal gate stacks.Type: GrantFiled: November 2, 2017Date of Patent: January 1, 2019Assignee: International Business Machines CorporationInventors: Dechao Guo, Liyang Song, Xinhui Wang, Qintao Zhang
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Publication number: 20180286760Abstract: A method is presented for creating an asymmetrical split-gate structure. The method includes forming a first device, forming a second device, forming a first gate stack between a first set of spacers of the first device, and a second gate stack between a second set of spacers of the second device. The method further includes depositing a hard mask over the first and second gate stacks, etching a first section of the first gate stack to create a first gap and a second section of the second gate stack to create a second gap, and forming a third gate stack within the first gap of the first gate stack and within the second gap of the second gate stack such that dual gate stacks are defined for each of the first and second devices. The method further includes annealing the dual gate stacks to form replacement metal gate stacks.Type: ApplicationFiled: April 3, 2017Publication date: October 4, 2018Inventors: Dechao Guo, Liyang Song, Xinhui Wang, Qintao Zhang
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Publication number: 20180286761Abstract: A method is presented for creating an asymmetrical split-gate structure. The method includes forming a first device, forming a second device, forming a first gate stack between a first set of spacers of the first device, and a second gate stack between a second set of spacers of the second device. The method further includes depositing a hard mask over the first and second gate stacks, etching a first section of the first gate stack to create a first gap and a second section of the second gate stack to create a second gap, and forming a third gate stack within the first gap of the first gate stack and within the second gap of the second gate stack such that dual gate stacks are defined for each of the first and second devices. The method further includes annealing the dual gate stacks to form replacement metal gate stacks.Type: ApplicationFiled: November 2, 2017Publication date: October 4, 2018Inventors: Dechao Guo, Liyang Song, Xinhui Wang, Qintao Zhang
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Patent number: 9484402Abstract: A method is disclosed for forming a semiconductor device. A first opening is formed for an STI on a semiconductor substrate and a first process is performed to deposit first oxide into the first opening. A second opening is formed to remove a portion of the first oxide from the first opening and second process(es) is/are performed to deposit second oxide into the second opening and over a remaining portion of the first oxide. A portion of the semiconductor device is formed over a portion of a surface of the second oxide. A semiconductor device includes an STI including a first oxide formed in a lower portion of a trench of the STI and a second oxide formed in an upper portion of the trench and above the first oxide. The semiconductor device includes a portion of the semiconductor device formed over a portion of the second oxide.Type: GrantFiled: March 19, 2015Date of Patent: November 1, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Ming Cai, Dechao Guo, Liyang Song, Chun-chen Yeh
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Patent number: 9397158Abstract: A method is disclosed for forming a semiconductor device. A first opening is formed for an STI on a semiconductor substrate and a first process is performed to deposit first oxide into the first opening. A second opening is formed to remove a portion of the first oxide from the first opening and second process(es) is/are performed to deposit second oxide into the second opening and over a remaining portion of the first oxide. A portion of the semiconductor device is formed over a portion of a surface of the second oxide. A semiconductor device includes an STI including a first oxide formed in a lower portion of a trench of the STI and a second oxide formed in an upper portion of the trench and above the first oxide. The semiconductor device includes a portion of the semiconductor device formed over a portion of the second oxide.Type: GrantFiled: March 19, 2015Date of Patent: July 19, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Ming Cai, Dechao Guo, Liyang Song, Chun-chen Yeh
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Publication number: 20150194334Abstract: A method is disclosed for forming a semiconductor device. A first opening is formed for an STI on a semiconductor substrate and a first process is performed to deposit first oxide into the first opening. A second opening is formed to remove a portion of the first oxide from the first opening and second process(es) is/are performed to deposit second oxide into the second opening and over a remaining portion of the first oxide. A portion of the semiconductor device is formed over a portion of a surface of the second oxide. A semiconductor device includes an STI including a first oxide formed in a lower portion of a trench of the STI and a second oxide formed in an upper portion of the trench and above the first oxide. The semiconductor device includes a portion of the semiconductor device formed over a portion of the second oxide.Type: ApplicationFiled: March 19, 2015Publication date: July 9, 2015Inventors: Ming Cai, Dechao Guo, Liyang Song, Chun-chen Yeh
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Publication number: 20150194484Abstract: A method is disclosed for forming a semiconductor device. A first opening is formed for an STI on a semiconductor substrate and a first process is performed to deposit first oxide into the first opening. A second opening is formed to remove a portion of the first oxide from the first opening and second process(es) is/are performed to deposit second oxide into the second opening and over a remaining portion of the first oxide. A portion of the semiconductor device is formed over a portion of a surface of the second oxide. A semiconductor device includes an STI including a first oxide formed in a lower portion of a trench of the STI and a second oxide formed in an upper portion of the trench and above the first oxide. The semiconductor device includes a portion of the semiconductor device formed over a portion of the second oxide.Type: ApplicationFiled: March 19, 2015Publication date: July 9, 2015Inventors: Ming Cai, Dechao Guo, Liyang Song, Chun-chen Yeh
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Patent number: 9059244Abstract: A method is disclosed for forming a semiconductor device. A first opening is formed for an STI on a semiconductor substrate and a first process is performed to deposit first oxide into the first opening. A second opening is formed to remove a portion of the first oxide from the first opening and second process(es) is/are performed to deposit second oxide into the second opening and over a remaining portion of the first oxide. A portion of the semiconductor device is formed over a portion of a surface of the second oxide. A semiconductor device includes an STI including a first oxide formed in a lower portion of a trench of the STI and a second oxide formed in an upper portion of the trench and above the first oxide. The semiconductor device includes a portion of the semiconductor device formed over a portion of the second oxide.Type: GrantFiled: October 15, 2013Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: Ming Cai, Dechao Guo, Liyang Song, Chun-chen Yeh
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Patent number: 9040399Abstract: A structure includes a substrate; a transistor disposed over the substrate, the transistor comprising a fin comprised of Silicon that is implanted with Carbon; and a gate dielectric layer and gate metal layer overlying a portion of the fin that defines a channel of the transistor. In the structure a concentration of Carbon within the fin is selected to establish a desired voltage threshold of the transistor. Methods to fabricate a FinFET transistor are also disclosed. Also disclosed is a planar transistor having a Carbon-implanted well where the concentration of the Carbon within the well is selected to establish a desired voltage threshold of the transistor.Type: GrantFiled: October 27, 2011Date of Patent: May 26, 2015Assignee: International Business Machines CorporationInventors: MaryJane Brodsky, Ming Cai, Dechao Guo, William K. Henson, Shreesh Narasimha, Yue Liang, Liyang Song, Yanfeng Wang, Chun-Chen Yeh
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Publication number: 20150102453Abstract: A method is disclosed for forming a semiconductor device. A first opening is formed for an STI on a semiconductor substrate and a first process is performed to deposit first oxide into the first opening. A second opening is formed to remove a portion of the first oxide from the first opening and second process(es) is/are performed to deposit second oxide into the second opening and over a remaining portion of the first oxide. A portion of the semiconductor device is formed over a portion of a surface of the second oxide. A semiconductor device includes an STI including a first oxide formed in a lower portion of a trench of the STI and a second oxide formed in an upper portion of the trench and above the first oxide. The semiconductor device includes a portion of the semiconductor device formed over a portion of the second oxide.Type: ApplicationFiled: October 15, 2013Publication date: April 16, 2015Applicant: International Business Machines CorporationInventors: Ming Cai, Dechao Guo, Liyang Song, Chun-chen Yeh
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Patent number: 8957464Abstract: A method for fabricating a transistor with uniaxial stress channels includes depositing an insulating layer onto a substrate, defining bars within the insulating layer, recessing a channel into the substrate, growing a first semiconducting material in the channel, defining a gate stack over the bars and semiconducting material, defining source and drain recesses and embedding a second semiconducting material into the source and drain recesses.Type: GrantFiled: January 14, 2014Date of Patent: February 17, 2015Assignee: International Business Machines CorporationInventors: Ming Cai, Dechao Guo, Liyang Song, Chun-Chen Yeh
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Patent number: 8927364Abstract: A method of forming a complementary metal oxide semiconductor (CMOS) device including an n-type field effect transistor (NFET) and an p-type field effect transistor (PFET) having fully silicided gates electrode in which an improved dual stress buried insulator is employed to incorporate and advantageous mechanical stress into the device channel of the NFET and PFET. The method can be imposed on a bulk substrate or extremely thin silicon on insulator (ETSOI) substrate. The device includes a semiconductor substrate, a plurality of shallow trench isolations structures formed in the ETSOI layer, NFET having a source and drain region and a gate formation, a PFET having a source and drain region, and a gate formation, an insulator layer, including a stressed oxide or nitride, deposited inside the substrate of the NFET, and a second insulator layer, including either an stressed oxide or nitride, deposited inside the substrate of the PFET.Type: GrantFiled: April 10, 2012Date of Patent: January 6, 2015Assignee: International Business Machines CorporationInventors: Ming Cai, Dechao Guo, Liyang Song, Chun-Chen Yeh
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Publication number: 20150001625Abstract: A method of forming a complementary metal oxide semiconductor (CMOS) device including an n-type field effect transistor (NFET) and an p-type field effect transistor (PFET) having fully silicided gates electrode in which an improved dual stress buried insulator is employed to incorporate and advantageous mechanical stress into the device channel of the NFET and PFET. The method can be imposed on a bulk substrate or extremely thin silicon on insulator (ETSOI) substrate. The device includes a semiconductor substrate, a plurality of shallow trench isolations structures formed in the ETSOI layer, NFET having a source and drain region and a gate formation, a PFET having a source and drain region, and a gate formation, an insulator layer, including a stressed oxide or nitride, deposited inside the substrate of the NFET, and a second insulator layer, including either an stressed oxide or nitride, deposited inside the substrate of the PFET.Type: ApplicationFiled: September 19, 2014Publication date: January 1, 2015Inventors: Ming Cai, Dechao Guo, Liyang Song, Chun-chen Yeh
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Publication number: 20140124861Abstract: A method for fabricating a transistor with uniaxial stress channels includes depositing an insulating layer onto a substrate, defining bars within the insulating layer, recessing a channel into the substrate, growing a first semiconducting material in the channel, defining a gate stack over the bars and semiconducting material, defining source and drain recesses and embedding a second semiconducting material into the source and drain recesses.Type: ApplicationFiled: January 14, 2014Publication date: May 8, 2014Applicant: International Business Machines CorporationInventors: Ming Cai, Dechao Guo, Liyang Song, Chun-Chen Yeh
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Patent number: 8633077Abstract: A method for fabricating a transistor with uniaxial stress channels includes depositing an insulating layer onto a substrate, defining bars within the insulating layer, recessing a channel into the substrate, growing a first semiconducting material in the channel, defining a gate stack over the bars and semiconducting material, defining source and drain recesses and embedding a second semiconducting material into the source and drain recesses.Type: GrantFiled: February 15, 2012Date of Patent: January 21, 2014Assignee: International Business Machines CorporationInventors: Ming Cai, Dechao Guo, Liyang Song, Chun-Chen Yeh
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Publication number: 20130330899Abstract: A method of forming gate stack structure for a transistor device includes forming a gate dielectric layer over a substrate; forming a first silicon gate layer over the gate dielectric layer; forming a dopant-rich monolayer over the first silicon gate layer; and forming a second silicon gate layer over the dopant-rich monolayer, wherein the dopant-rich monolayer prevents silicidation of the first silicon gate layer during silicidation of the second silicon gate layer.Type: ApplicationFiled: June 19, 2012Publication date: December 12, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Huiming Bu, Ming Cai, Kevin K. Chan, Dechao Guo, Ravikumar Ramachandran, Liyang Song, Chun-Chen Yeh
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Publication number: 20130328135Abstract: A gate stack structure for a transistor device includes a gate dielectric layer formed over a substrate; a first silicon gate layer formed over the gate dielectric layer; a dopant-rich monolayer formed over the first silicon gate layer; and a second silicon gate layer formed over the dopant-rich monolayer, wherein the dopant-rich monolayer prevents silicidation of the first silicon gate layer during silicidation of the second silicon gate layer.Type: ApplicationFiled: June 12, 2012Publication date: December 12, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Huiming Bu, Ming Cai, Kevin K. Chan, Dechao Guo, Ravikumar Ramachandran, Liyang Song, Chun-Chen Yeh