Abstract: A method for cutting off a fin in a field effect transistor, comprising: step 1: forming fins and first spacing regions, there are two types of fins—the first type is configured to be cut off and a second type is configured to be reserved; and forming a first material layer to fill the first spacing regions; step 2: forming a first pattern structure comprising first strip structures aligning to one first type fin and second spacing regions; step 3: forming second sidewalls on two sides of each first strip structure; step 4: removing the first strip structures to form a second pattern structure by the second sidewalls; step 5: etching away the first material layer and the first type of fins by using the second sidewalls as a mask ; step 6: removing the second sidewalls and the remaining first material layer. The present application enables using less advanced lithography equipment.

Abstract: The present disclosure discloses a FinFET transistor cut etching process method, comprising: step 1, forming a first photoresist pattern to define a cut etching region of the FinFET transistor; step 2, forming a second amorphous semiconductor pattern; step 3, forming a first dielectric layer and a first groove; step 4, forming a second dielectric layer that fully fills the first groove; step 5, performing CMP using the second amorphous semiconductor layer as a stop layer, so as to form a sidewall and a second dielectric layer strip; step 6, performing self-alignment to remove each side wall; step 7, performing a wet process to remove the amorphous semiconductor strip; and step 8: performing etching by using each second dielectric layer strip as a mask, so as to form a fin and achieve cut etching of the FinFET transistor. The present disclosure can enlarge the process window and reduce the process cost.

Abstract: The present application discloses a metal gate which is formed by replacing a polysilicon pseudo-gate. First a gate trench is created after the polysilicon pseudo-gate is removed. The gate trench is divided into atop trench and a bottom trench. A first sidewall of the polysilicon pseudo-gate is partially remove to the level of the top trench depth and it is then replaced with a second sidewall with a smaller width, such that the width of the top trench is expanded from the width of the first sidewall to the width of the second sidewall, so that the top trench is wider than the bottom trench. The metal gate is then disposed in the gate trench. A method for manufacturing the metal gate is also disclosed. The present application can improve the metal gate filling process window and eliminate the void left by the current metal gate filling process.

Abstract: Provided is a method for manufacturing a 14 nm-node BEOL 32 nm-width metal. A semiconductor structure for manufacturing BEOL wire is provided, wherein the semiconductor structure at least comprises a carbon coating and intermediate layer on it; forming a photoresist layer on the intermediate layer and exposing the photoresist layer according to a layout; developing the exposed photoresist layer by using a developing solution, and causing the developed photoresist to react with the intermediate layer in a contact region of the developed photoresist to form a peg groove; and etching by using the groove in the semiconductor structure to form a 14 nm-node BEOL 32 nm-width metal. This application can reducing the longitudinal shrink of the metal wire, achieving the improvement of the lateral and longitudinal shrink uniformity, reducing defects caused by misalignment of the through hole and the metal wire, and increasing the effective usable area of a chip.

Abstract: The present disclosure relates to a FinFET and a manufacturing method of a contact. The manufacturing method comprises steps of: sequentially generating an interlayer dielectric layer, a metal hard mask, an oxide protective cap and a tri-layer mask on a gate to form a device to be etched; photoetching the tri-layer mask to remove photoresist in a non-patterned area; performing main etch on the device to be etched after the photoetching to remove the interlayer dielectric layer in the area that is not covered by the metal hard mask, and the metal hard mask is provided with the oxide protective cap; performing ODL removal on the device to be etched after the main etch to remove remaining part of the tri-layer mask; performing oxide etch on the device to be etched after the ODL removal to remove the oxide protective cap; and generating the contact on the device after the oxide etch. The present disclosure can accurately control the critical dimensions of the contact in an X direction and a Y direction.

Abstract: A method for cutting off a fin in a field effect transistor, comprising: step 1: forming fins and first spacing regions, there are two types of fins—the first type is configured to be cut off and a second type is configured to be reserved; and forming a first material layer to fill the first spacing regions; step 2: forming a first pattern structure comprising first strip structures aligning to one first type fin and second spacing regions; step 3: forming second sidewalls on two sides of each first strip structure; step 4: removing the first strip structures to form a second pattern structure by the second sidewalls; step 5: etching away the first material layer and the first type of fins by using the second sidewalls as a mask ; step 6: removing the second sidewalls and the remaining first material layer. The present application enables using less advanced lithography equipment.

Abstract: The disclosure provides a method for making a self-aligned double pattern, A silicon substrate with a first oxide layer, an amorphous silicon layer and an organic layer, etching the organic layer and the amorphous silicon layer, and covering them with a first silicon nitride layer; remove the first silicon nitride layer in the amorphous silicon pattern, forming first silicon nitride sidewall patterns on the amorphous silicon pattern's sidewalls; removing the amorphous silicon pattern between the first silicon nitride sidewall patterns; defining the morphology of a fin field-effect transistor, form core patterns and covering them with a thin silicon nitride layer; depositing a second oxide layer; defining the fin field-effect transistor's height, and etching back the second oxide layer till the height of the core patterns satisfies the defined fin field-effect transistor height; removing the thin silicon nitride layer, depositing a third oxide layer to cover the core patterns.

Abstract: The disclosure provides a method for making a self-aligned double pattern, A silicon substrate with a first oxide layer, an amorphous silicon layer and an organic layer, etching the organic layer and the amorphous silicon layer, and covering them with a first silicon nitride layer; remove the first silicon nitride layer in the amorphous silicon pattern, forming first silicon nitride sidewall patterns on the amorphous silicon pattern's sidewalls; removing the amorphous silicon pattern between the first silicon nitride sidewall patterns; defining the morphology of a fin field-effect transistor, form core patterns and covering them with a thin silicon nitride layer; depositing a second oxide layer; defining the fin field-effect transistor's height, and etching back the second oxide layer till the height of the core patterns satisfies the defined fin field-effect transistor height; removing the thin silicon nitride layer, depositing a third oxide layer to cover the core patterns.

Abstract: This disclosure discloses a process method for cutting a polysilicon gate of a FinFET transistor, comprising: step 1, forming a fin and a first groove in a polysilicon gate formation region and forming a second groove in a non-polysilicon gate region; step 2, performing filing with a first insulating layer; step 3, performing definition by using a second photomask opposite to a first photomask that defines a polysilicon gate cutting region, and forming a first mask on the top of the first insulating layer in the second groove; step 4, performing etching-back of the first insulating layer to define the height of the fin; step 5, forming a polysilicon gate; and step 6, after the polysilicon gate cutting region is opened by using the first photomask, performing polysilicon etching to achieve cutting of the polysilicon gate. In the present disclosure, the process window is enlarged, thereby increasing the product yield.

Abstract: The present disclosure relates to a FinFET and a manufacturing method of a contact. The manufacturing method comprises steps of: sequentially generating an interlayer dielectric layer, a metal hard mask, an oxide protective cap and a tri-layer mask on a gate to form a device to be etched; photoetching the tri-layer mask to remove photoresist in a non-patterned area; performing main etch on the device to be etched after the photoetching to remove the interlayer dielectric layer in the area that is not covered by the metal hard mask, and the metal hard mask is provided with the oxide protective cap; performing ODL removal on the device to be etched after the main etch to remove remaining part of the tri-layer mask; performing oxide etch on the device to be etched after the ODL removal to remove the oxide protective cap; and generating the contact on the device after the oxide etch. The present disclosure can accurately control the critical dimensions of the contact in an X direction and a Y direction.

Abstract: This disclosure discloses a process method for cutting a polysilicon gate of a FinFET transistor, comprising: step 1, forming a fin and a first groove in a polysilicon gate formation region and forming a second groove in a non-polysilicon gate region; step 2, performing filing with a first insulating layer; step 3, performing definition by using a second photomask opposite to a first photomask that defines a polysilicon gate cutting region, and forming a first mask on the top of the first insulating layer in the second groove; step 4, performing etching-back of the first insulating layer to define the height of the fin; step 5, forming a polysilicon gate; and step 6, after the polysilicon gate cutting region is opened by using the first photomask, performing polysilicon etching to achieve cutting of the polysilicon gate. In the present disclosure, the process window is enlarged, thereby increasing the product yield.

Abstract: The present disclosure discloses a FinFET transistor cut etching process method, comprising: step 1, forming a first photoresist pattern to define a cut etching region of the FinFET transistor; step 2, forming a second amorphous semiconductor pattern; step 3, forming a first dielectric layer and a first groove; step 4, forming a second dielectric layer that fully fills the first groove; step 5, performing CMP using the second amorphous semiconductor layer as a stop layer, so as to form a sidewall and a second dielectric layer strip; step 6, performing self-alignment to remove each side wall; step 7, performing a wet process to remove the amorphous semiconductor strip; and step 8: performing etching by using each second dielectric layer strip as a mask, so as to form a fin and achieve cut etching of the FinFET transistor. The present disclosure can enlarge the process window and reduce the process cost.

Abstract: Provided is a method for manufacturing a 14 nm-node BEOL 32 nm-width metal. A semiconductor structure for manufacturing BEOL wire is provided, wherein the semiconductor structure at least comprises a carbon coating and intermediate layer on it; forming a photoresist layer on the intermediate layer and exposing the photoresist layer according to a layout; developing the exposed photoresist layer by using a developing solution, and causing the developed photoresist to react with the intermediate layer in a contact region of the developed photoresist to form a peg groove; and etching by using the groove in the semiconductor structure to form a 14 nm-node BEOL 32 nm-width metal. This application can reducing the longitudinal shrink of the metal wire, achieving the improvement of the lateral and longitudinal shrink uniformity, reducing defects caused by misalignment of the through hole and the metal wire, and increasing the effective usable area of a chip.