Patents by Inventor Liz Poliak

Liz Poliak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11843043
    Abstract: A method fabricating a GaN based sensor including: forming a gate dielectric layer over a GaN hetero-structure including a GaN layer formed over a substrate and a first barrier layer formed over the GaN layer; forming a first mask over the gate dielectric layer; etching the gate dielectric layer and the first barrier layer through the first mask, thereby forming source and drain contact openings; removing the first mask; forming a metal layer over the gate dielectric layer, wherein the metal layer extends into the source and drain contact openings; forming a second mask over the metal layer; etching the metal layer, the gate dielectric layer and the GaN heterostructure through the second mask, wherein a region of the GaN heterostructure is exposed; and thermally activating the metal layer in the source and drain contact openings. The gate dielectric may exhibit a sloped profile, and dielectric spacers may be formed.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: December 12, 2023
    Assignee: Tower Semiconductor Ltd.
    Inventors: Ruth Shima-Edelstein, Ronen Shaul, Roy Strul, Anatoly Sergienko, Liz Poliak, Ido Gilad, Alex Sirkis, Yakov Roizin
  • Publication number: 20220059675
    Abstract: A method fabricating a GaN based sensor including: forming a gate dielectric layer over a GaN hetero-structure including a GaN layer formed over a substrate and a first barrier layer formed over the GaN layer; forming a first mask over the gate dielectric layer; etching the gate dielectric layer and the first barrier layer through the first mask, thereby forming source and drain contact openings; removing the first mask; forming a metal layer over the gate dielectric layer, wherein the metal layer extends into the source and drain contact openings; forming a second mask over the metal layer; etching the metal layer, the gate dielectric layer and the GaN heterostructure through the second mask, wherein a region of the GaN heterostructure is exposed; and thermally activating the metal layer in the source and drain contact openings. The gate dielectric may exhibit a sloped profile, and dielectric spacers may be formed.
    Type: Application
    Filed: November 4, 2021
    Publication date: February 24, 2022
    Inventors: Ruth Shima-Edelstein, Ronen Shaul, Roy Strul, Anatoly Sergienko, Liz Poliak, Ido Gilad, Alex Sirkis, Yakov Roizin
  • Patent number: 11195933
    Abstract: A method fabricating a GaN based sensor including: forming a gate dielectric layer over a GaN hetero-structure including a GaN layer formed over a substrate and a first barrier layer formed over the GaN layer; forming a first mask over the gate dielectric layer; etching the gate dielectric layer and the first barrier layer through the first mask, thereby forming source and drain contact openings; removing the first mask; forming a metal layer over the gate dielectric layer, wherein the metal layer extends into the source and drain contact openings; forming a second mask over the metal layer; etching the metal layer, the gate dielectric layer and the GaN heterostructure through the second mask, wherein a region of the GaN heterostructure is exposed; and thermally activating the metal layer in the source and drain contact openings. The gate dielectric may exhibit a sloped profile, and dielectric spacers may be formed.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: December 7, 2021
    Assignee: Tower Semiconductor Ltd.
    Inventors: Ruth Shima-Edelstein, Ronen Shaul, Roy Strul, Anatoly Sergienko, Liz Poliak, Ido Gilad, Alex Sirkis, Yakov Roizin
  • Publication number: 20210242326
    Abstract: A method fabricating a GaN based sensor including: forming a gate dielectric layer over a GaN hetero-structure including a GaN layer formed over a substrate and a first barrier layer formed over the GaN layer; forming a first mask over the gate dielectric layer; etching the gate dielectric layer and the first barrier layer through the first mask, thereby forming source and drain contact openings; removing the first mask; forming a metal layer over the gate dielectric layer, wherein the metal layer extends into the source and drain contact openings; forming a second mask over the metal layer; etching the metal layer, the gate dielectric layer and the GaN heterostructure through the second mask, wherein a region of the GaN heterostructure is exposed; and thermally activating the metal layer in the source and drain contact openings. The gate dielectric may exhibit a sloped profile, and dielectric spacers may be formed.
    Type: Application
    Filed: February 4, 2020
    Publication date: August 5, 2021
    Inventors: Ruth Shima-Edelstein, Ronen Shaul, Roy Strul, Anatoly Sergienko, Liz Poliak, Ido Gilad, Alex Sirkis, Yakov Roizin