Abstract: The present invention relates to the field of biomedicine, specifically to a monoclonal antibody targeting SIRP?, and a preparation method and the use thereof. The SIRP? antibody or the antigen-binding portion thereof prepared by the present invention has a high affinity for SIRP? and a low affinity for SIRP?, which differ by two orders of magnitude. The SIRP? antibody or the antigen-binding portion thereof can efficiently block the binding of CD47 to SIRP?-V1, SIRP?-V2 and SIRP?-V8, thereby promoting the activation of macrophages, particularly enhancing the regulatory antibody-dependent cellular phagocytosis (ADCP) of a target tumor cell, bridging about innate and adaptive immune responses, and promoting the synergistic anti-cancer effect of the SIRP? antibody or the antigen-binding portion thereof with a checkpoint inhibitor PD-(L)1 monoclonal antibody. The antibody can be used for treating various cancers and microbial infectious diseases.

Abstract: An array substrate and a display device are provided. The array substrate includes: a substrate, sub-pixel units, first signal lines, and second signal lines; multiple first signal lines and multiple second signal lines intersect to define the opening areas of the sub-pixel units; each second signal line includes: multiple first parts extending along the column direction, and multiple second parts; the second part includes a portion extending along the inclination direction, and the second part connects two first parts; the angle between the inclination direction and the column direction or row direction is greater than 0; each first part is adjacent to the opening area of the sub-pixel units in the row direction, and multiple second parts respectively pass through at least of the areas between adjacent two pixel repeating unit rows, with the distance between the two first parts being greater than 0 in the row direction.

Abstract: A method for installing a maximum power point tracking (MPPT) controller is provided. The method includes acquiring an occlusion area proportion of a photovoltaic string in a photovoltaic system, optimizing the occlusion area proportion to generate a target occlusion area proportion, determining a target position from the photovoltaic string according to the target occlusion area proportion, and installing the MPPT controller at the target position.

Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.

Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.

Abstract: A memory redundancy reconfiguration for N base blocks associated with k redundant blocks. The data will be written into both base blocks and defect-free redundant blocks if the base blocks are defective; k multiplexers MUXRi each having N input signals (d0 to dN?1) capable of being connected to k input signals of the redundant blocks; N multiplexers MUXi each having k+1 input signals from k redundant blocks (R0 to Rk?1) and one base block (Ni), capable of being connected to N output signals (qi); and logic means associated with each multiplexer, to convert the input signals of the multiplexer to its output signal.

Abstract: A memory redundancy reconfiguration for N base blocks associated with k redundant blocks. The data will be written into both base blocks and defect-free redundant blocks if the base blocks are defective; k multiplexers MUXRi each having N input signals (d0 to dN?1) capable of being connected to k input signals of the redundant blocks; N multiplexers MUXi each having k+1 input signals from k redundant blocks (R0 to Rk?1) and one base block (Ni), capable of being connected to N output signals (qi); and logic means associated with each multiplexer, to convert the input signals of the multiplexer to its output signal.