Abstract: Disclosed is a downhole fluid resistivity sensor that includes a ceramic cylinder having a fluid-contacting surface, and at least four metal pins that penetrate a wall of the ceramic cylinder at axially-spaced locations. The pins are bonded to the ceramic to form a pressure seal. The sensor may include a circuit that injects current into a fluid via an outer two of the pins, and measures a resulting voltage via an inner two of the pins. The circuit may also provide an indication of fluid resistivity based at least in part on the resulting voltage. At each of the axially-spaced locations, a set of multiple pins may penetrate the wall to contact the fluid at circumferentially-spaced positions. The fluid-contacting surface may be an inner surface or an outer surface of the ceramic cylinder. A downhole fluid resistivity measurement method is also described.

Abstract: In some embodiments, an apparatus and a system, as well as a method and an article, may operate to advance a sampling and guard probe (100) with a surrounding sealing pad (108) against a borehole wall, to adjust the size of the area associated with a fluid flow inlet of the probe, where the size of the inlet area (104) is selectably and incrementally variable, and to draw fluid into the fluid flow inlet by activating at least one pump (344) coupled to at least one fluid passage (128) in the probe. Additional apparatus, systems, and methods are disclosed.

Abstract: Methods and systems for improving operations of a formation tester are disclosed. The formation tester (400) is placed in a wellbore at a location of interest. The formation tester comprises a first isolation pad (402) coupled to a pad carrier (410) and a second isolation pad (404). The first isolation is extendable to substantially seal a probe of the formation tester against a well bore wall. The first isolation pad is then replaced with the second isolation pad if it is determined that the first isolation pad should be replaced with the second isolation pad.

Abstract: Statistical timing analysis methods for circuits having latches and feedback loops are described wherein the circuit yield, and/or the critical cycle mean (the largest cycle mean among all loops in the circuit), may be iteratively calculated with high speed and accuracy, thereby allowing their ready usage in the analysis and validation of proposed circuit designs.

Abstract: A method is provided to evaluate crosstalk effect of aggressor switching upon victim net signal transition time within an integrated circuit comprising: combining a first probability density function (PDF) of first aggressor switching time in response to a first input signal to an aggressor net driver and a second aggressor switching time in response to a second input signal to the aggressor net driver; determining a delay change curve that represents a relationship between delay change of arrival time of a victim net signal transition and relative alignment of the aggressor net driver switching time and a victim net driver switching time; and determining a third PDF of delay change of a transition of the victim net signal based upon the combination and the delay change curve.

Abstract: A method, system, and computer program product are disclosed for performing statistical leakage power characterization to estimate yield of a circuit in terms of leakage power. According to some approaches, this is performed with consideration of state correlation.

Abstract: A method, system, and computer program product are disclosed for performing statistical leakage power characterization to estimate yield of a circuit in terms of leakage power. According to some approaches, this is performed with consideration of bi-exponential modeling.

Abstract: Statistical timing analysis methods for circuits having latches and feedback loops are described wherein the circuit yield, and/or the critical cycle mean (the largest cycle mean among all loops in the circuit), may be iteratively calculated with high speed and accuracy, thereby allowing their ready usage in the analysis and validation of proposed circuit designs.

Abstract: Statistical timing analysis methods for circuits having latches and feedback loops are described wherein the circuit yield, and/or the critical cycle mean (the largest cycle mean among all loops in the circuit), may be iteratively calculated with high speed and accuracy, thereby allowing their ready usage in the analysis and validation of proposed circuit designs.

Abstract: Method and system for crosstalk analysis relating to a statistical crosstalk path delay model that fits into existing static timing framework with little overhead in performance and capacity. More realistic models or assumptions are utilized rather than the more aggressive and less likely deterministic model.

Abstract: A method, system, and computer program product are disclosed for performing statistical leakage power characterization to estimate yield of a circuit in terms of leakage power. According to some approaches, this is performed with consideration of bi-exponential modeling.

Abstract: Statistical timing analysis methods for circuits are described which compensate for circuit elements having correlated timing delays with a high degree of computational efficiency. An quadratic timing model is used to represent each delay element along a circuit path, wherein each element's delay has a first-order relationship to local variations and a second-order relationship to global variations. Propagation of the modeled delays through the circuit is efficiently done via straightforward ADD operations where an input propagates through another element in a circuit path, and via a MAX operation (or an approximation thereof) where two or more inputs merge at an intersection. The inputs to the MAX operator can be tested for gaussianity, and can be processed by the MAX operation (or its approximation) if they are substantially gaussian. Otherwise, they may be stored in a tuple for processing at later points along the circuit path.

Abstract: A method, system, and computer program product are disclosed for performing statistical leakage power characterization to estimate yield of a circuit in terms of leakage power. According to some approaches, this is performed with consideration of state correlation.

Abstract: Statistical timing analysis methods for circuits having latches and feedback loops are described wherein the circuit yield, and/or the critical cycle mean (the largest cycle mean among all loops in the circuit), may be iteratively calculated with high speed and accuracy, thereby allowing their ready usage in the analysis and validation of proposed circuit designs.

Abstract: Embodiments of inspection systems and methods are disclosed. One embodiment of an inspection system, among others, comprises logic configured to receive a reference signal and a target signal, the reference signal having first surface displacement information and the target signal having second surface displacement information, said logic configured to determine a correlation coefficient between the first surface displacement information and the second surface displacement information, the correlation coefficient indicating whether an inspected object exhibits a defect.

Abstract: Statistical timing analysis methods for circuits are described which compensate for circuit elements having correlated timing delays with a high degree of computational efficiency. An extended canonical timing model is used to represent each delay element along a circuit path, wherein the model bears information regarding any correlations that each element has to any other elements in the circuit (and/or to any external global factors, e.g., global temperature variations over the circuit, etc.). The model can be represented in a vectorized format which allows enhancement of computational efficiency, wherein the coefficients of the vectors allow an objective measure of element correlation (and wherein the vectors can be “pruned” by dropping insignificant coefficients to further enhance computational efficiency). A decomposition procedure can be used to decompose correlated elements into uncorrelated elements to allow delays to me more easily propagated through the timing diagram representing the circuit.

Abstract: Statistical timing analysis methods for circuits are described which compensate for circuit elements having correlated timing delays with a high degree of computational efficiency. An quadratic timing model is used to represent each delay element along a circuit path, wherein each element's delay has a first-order relationship to local variations and a second-order relationship to global variations. Propagation of the modeled delays through the circuit is efficiently done via straightforward ADD operations where an input propagates through another element in a circuit path, and via a MAX operation (or an approximation thereof) where two or more inputs merge at an intersection. The inputs to the MAX operator can be tested for gaussianity, and can be processed by the MAX operation (or its approximation) if they are substantially gaussian. Otherwise, they may be stored in a tuple for processing at later points along the circuit path.

Abstract: The invention provides a method, system, and program product for accommodating spatially-correlated variation in a process parameter during statistical timing of a circuit. In one embodiment, the method includes dividing an area of the circuit into a plurality of grid cells; associating an independent random variable with each of the plurality of grid cells; and expressing at least one spatially-correlated parameter of a first grid cell as a function of the random variables associated with the first grid cell and at least one neighboring grid cell.

Abstract: Statistical timing analysis methods for circuits are described which compensate for circuit elements having correlated timing delays with a high degree of computational efficiency. An extended canonical timing model is used to represent each delay element along a circuit path, wherein the model bears information regarding any correlations that each element has to any other elements in the circuit (and/or to any external global factors, e.g., global temperature variations over the circuit, etc.). The model can be represented in a vectorized format which allows enhancement of computational efficiency, wherein the coefficients of the vectors allow an objective measure of element correlation (and wherein the vectors can be “pruned” by dropping insignificant coefficients to further enhance computational efficiency). A decomposition procedure can be used to decompose correlated elements into uncorrelated elements to allow delays to me more easily propagated through the timing diagram representing the circuit.

Abstract: The invention provides a method, system, and program product for accommodating spatially-correlated variation in a process parameter during statistical timing of a circuit. In one embodiment, the method includes dividing an area of the circuit into a plurality of grid cells; associating an independent random variable with each of the plurality of grid cells; and expressing at least one spatially-correlated parameter of a first grid cell as a function of the random variables associated with the first grid cell and at least one neighboring grid cell.