Abstract: The present disclosure provides a display substrate, a display panel and a display apparatus. The display substrate includes a first base substrate; a plurality of gate lines and a plurality of data lines which are arranged on a side of the first base substrate; the plurality of gate lines and the plurality of data lines are arranged to be intersected with each other and insulated from each other; a planarization layer, arranged on a side of the gate lines and the data lines away from the first base substrate, and including a first via hole; and a supporting structure, arranged on a side of the planarization layer away from the first base substrate and filled into the first via hole; and in a direction perpendicular to the first base substrate, a height of the supporting structure is greater than a depth of the first via hole.

Abstract: The present disclosure provides a display substrate, a display panel and a display apparatus. The display substrate includes a base substrate; a transistor, located on the base substrate, and including an active layer; and a data line, located between the active layer and the base substrate; the data line is connected with the active layer, and an orthographic projection of the active layer on the base substrate is located in an orthographic projection of the data line on the base substrate.

Abstract: A display panel is disclosed. In the display panel, the second electrode is electrically connected to the first electrode through the first via hole, and a first support structure is provided in a region corresponding to the first via hole; and at least a part of the first support structure is located in the first via hole, and an orthographic projection of the first via hole on the base substrate at least partially overlaps with an orthographic projection of the gate line on the base substrate, the first support structure extends upward within the first via hole to an upper opening region of the first via hole, and a top of the first support structure is higher than the upper surface of the first interlayer insulating layer, a surface of the first support structure close to the second substrate is a curved surface.

Abstract: Provided is a substrate. The substrate includes a base substrate; and a plurality of sub-pixel structures arranged in an array on the base substrate, wherein the sub-pixel structure comprises: a thin film transistor disposed on the base substrate, the thin film transistor comprising a source and a drain; an insulating layer disposed on a side of the thin film transistor distal from the base substrate, a first via hole being formed in the insulating layer; a pixel electrode disposed on a side of the insulating layer distal from the base substrate, the pixel electrode being electrically connected to either the source or the drain through the first via hole; and a filling block disposed at the first via hole.

Abstract: A displaying base plate and a displaying device are provided by the present application, wherein the displaying base plate includes a substrate, and a first electrode layer disposed on one side of the substrate, wherein the first electrode layer includes a first electrode pattern; a first planarization layer disposed on one side of the first electrode layer that is away from the substrate, wherein the first planarization layer is provided with a through hole, and the through hole penetrates the first planarization layer, to expose the first electrode pattern; and a second electrode layer, a second planarization layer and a third electrode layer that are disposed in stack on one side of the first planarization layer that is away from the substrate.

Abstract: The present disclosure provides a thin film transistor, a GOA circuit and an array substrate, the thin film transistor comprising: a source electrode, including a source electrode wiring and a plurality of source electrode branches; a drain electrode, including a drain electrode wiring and a plurality of drain electrode branches; a gate; a semiconductor layer comprising a plurality of semiconductor branches; a plurality of source electrode branches, wherein the plurality of drain electrode branches are in contact with the plurality of semiconductor branches and are divided into a plurality of cells; the source electrode wiring and the drain electrode wiring are arranged in a parallel and spaced apart, and the number m of one of the source electrode wiring and the drain electrode wiring is an integer greater than or equal to 2, and the number n of the other is an integer greater than or equal to 1.

Abstract: A video encoding method includes: based on at least one of first distortion aware information about a current encoding unit and second distortion aware information about a corresponding reference encoding unit, determining a first predicted value of the current encoding unit using at least one interpolation filter, wherein the at least one type of interpolation filter may include an artificial intelligence (AI) interpolation filter; and encoding the current encoding unit based on the first predicted value of the current encoding unit.

Abstract: At least one embodiment of the present disclosure provides a display panel, and the display panel includes: a first substrate and a second substrate oppositely combined with each other, the first substrate includes a base substrate, and a gate line, a first electrode, a first interlayer insulating layer, and second electrode on the base substrate; the first interlayer insulating layer includes a first via hole penetrating through the first interlayer insulating layer, the second electrode is electrically connected to the first electrode the first via hole, first support structure is provided in a region corresponding to the first via hole and on a side of the second electrode away from the base substrate; at least a part of the first support structure is located in the first via hole, an orthographic projection of the first via hole overlaps with an orthographic projection of the gate line on the base substrate.

Abstract: An oxide thin film transistor, a preparation method thereof, and an electronic device are provided. The oxide thin film transistor includes a base substrate, a gate electrode and a metal oxide semiconductor layer, a gate insulation layer arranged between the metal oxide semiconductor layer and the gate electrode; the gate insulation layer includes a silicon oxide insulation layer and a silicon nitride layer, the silicon nitride layer adopts a single-layer structure or include a plurality of silicon nitride sublayers which are sequentially stacked, the silicon oxide insulation layer is between the silicon nitride layer and the metal oxide semiconductor layer; at least a part of a region in the silicon nitride layer satisfies that the percentage content of Si—H bonds in the sum of Si—N bonds, N—H bonds and Si—H bonds is not more than 7.

Abstract: An oxide thin film transistor includes: a gate electrode, a metal oxide active layer and a source-drain metal layer, which are on a base substrate. The metal oxide active layer includes a first metal oxide layer and a second metal oxide layer stacked on the first metal oxide layer in a direction away from the base substrate; the first metal oxide layer is a carrier transport layer; the second metal oxide layer is a carrier isolation layer; an electron transfer rate of the carrier transport layer is greater than an electron transfer rate of the carrier isolation layer. The first metal oxide layer includes a primary surface facing toward the base substrate and a primary surface away from the base substrate; the first metal oxide layer further includes a lateral surface around the primary surfaces; the second metal oxide layer covers the lateral surface of the first metal oxide layer.

Abstract: An array substrate, a method for manufacturing an array substrate, a liquid crystal cell and a display apparatus are provided. The array substrate includes: a first base substrate; thin film transistors; a first planarization layer; a common electrode on a side of the first planarization layer away from the thin film transistors; a first dielectric layer on a side of the common electrode away from the first planarization layer; first pixel electrodes on a side of the first dielectric layer away from the common electrode; the first pixel electrodes are electrically connected to the thin film transistors in a one-to-one correspondence through first vias extending through the first dielectric layer and the first planarization layer; a surface of each first pixel electrode away from the first base substrate is provided with a first groove at least corresponding to a corresponding first via.

Abstract: A thin film transistor, a shift register unit, a gate driving circuit and a display panel are provided. The M source branches and the N drain branches extend along a first direction and are arranged at intervals; in each of the P source-drain units, the M source branches and the N drain branches are alternately arranged, and M is greater than or equal to N; a semiconductor layer includes sub-channel regions between one drain branch and one source branch adjacent to each other; a sum of widths of the sub-channel regions of the P source-drain units in the first direction is W, and an average length of the sub-channel regions of the P source-drain units in a direction perpendicular to the first direction is L; 12?W/L?400, P, M and N are integers greater than or equal to 1, and P×N?4.

Abstract: Provided is a substrate. The substrate includes a base substrate; and a plurality of sub-pixel structures arranged in an array on the base substrate, wherein the sub-pixel structure comprises: a thin film transistor disposed on the base substrate, the thin film transistor comprising a source and a drain; an insulating layer disposed on a side of the thin film transistor distal from the base substrate, a first via hole being formed in the insulating layer; a pixel electrode disposed on a side of the insulating layer distal from the base substrate, the pixel electrode being electrically connected to either the source or the drain through the first via hole; and a filling block disposed at the first via hole.

Abstract: The present disclosure provides a display substrate, a display panel and a display apparatus. The display substrate includes a base substrate; a transistor, located on the base substrate, and including an active layer; and a data line, located between the active layer and the base substrate; the data line is connected with the active layer, and an orthographic projection of the active layer on the base substrate is located in an orthographic projection of the data line on the base substrate.

Abstract: A display substrate, a display panel and a display apparatus. The display substrate includes a first base substrate; a plurality of gate lines and a plurality of data lines which are arranged on a side of the first base substrate; the plurality of gate lines and the plurality of data lines are arranged to be intersected with each other and insulated from each other; a planarization layer, arranged on a side of the gate lines and the data lines away from the first base substrate, and including a first via hole; and a supporting structure, arranged on a side of the planarization layer away from the first base substrate and filled into the first via hole; and in a direction perpendicular to the first base substrate, a height of the supporting structure is greater than a depth of the first via hole.

Abstract: A displaying base plate and a manufacturing method thereof, and a displaying device. The displaying base plate includes a substrate, and a first electrode layer disposed on one side of the substrate, wherein the first electrode layer includes a first electrode pattern; a first planarization layer disposed on one side of the first electrode layer that is away from the substrate, wherein the first planarization layer is provided with a through hole, and the through hole penetrates the first planarization layer, to expose the first electrode pattern; and a second electrode layer, a second planarization layer and a third electrode layer that are disposed in stack on one side of the first planarization layer that is away from the substrate, wherein the second electrode layer is disposed closer to the substrate, the second electrode layer is connected to the first electrode pattern and the third electrode layer.

Abstract: The present disclosure provides a thin film transistor, a GOA circuit and an array substrate, the thin film transistor including a source electrode, including a source electrode wiring and a plurality of source electrode branches; a drain electrode, including a drain electrode wiring and a plurality of drain electrode branches; a gate; a semiconductor layer including a plurality of semiconductor branches; a plurality of source electrode branches. The plurality of drain electrode branches are in contact with the plurality of semiconductor branches and are divided into a plurality of cells; the source electrode wiring and the drain electrode wiring are arranged in a parallel and spaced apart, and the number m of one of the source electrode wiring and the drain electrode wiring is an integer greater than or equal to 2, and the number n of the other is an integer greater than or equal to 1.

Abstract: The disclosure provides a liquid crystal display panel and a display apparatus. The liquid crystal display panel of the disclosure includes: first and second substrates assembled to form a cell, a plurality of main spacers therebetween, and an auxiliary spacer around at least a portion of the main spacers. Height of the auxiliary spacer is greater than or equal to that of the main spacer. The display panel further includes: pillows on side of the first substrate close to the second substrate and each abutting against a corresponding main spacer. An orthographic projection of the main spacer on the first substrate falls within an orthographic projection of the pillow on the first substrate, and an orthographic projection of the auxiliary spacer on the first substrate does not overlap with the orthographic projection of the pillow on the first substrate.

Abstract: A display substrate, a manufacturing method thereof and a display apparatus are provided. In the present disclosure, a first transistor group with oxide semiconductor as an active layer material is disposed on a side of a second transistor group with polysilicon as an active layer material away from the base, and an area enclosed by orthographic projections of the transistors in the first transistor group on the base is overlapped with an area enclosed by orthographic projections of the transistors in the second transistor group on the base. Stable performance of the transistors included can be ensured in a manufacturing process of the first transistor group and the second transistor group located in different layers, and at the same time, an area occupied by the driving circuit can be reduced so as to decrease a frame width of a display apparatus or improve resolution of the display apparatus.

Abstract: The present disclosure provides a display substrate, a method for manufacturing the display substrate and a display panel. The display substrate includes: a first semiconductor layer on a base substrate, where an active layer of the first thin film transistor is in the first semiconductor layer, and the active layer of the first thin film transistor at least comprises a channel region and a drain contact region; an interlayer insulation layer on a side of the first semiconductor layer away from the base substrate; and a first conductive layer on a side of the interlayer insulation layer away from the first semiconductor layer, wherein the pixel electrode is located in the first conductive layer, and the pixel electrode in the pixel unit is directly and electrically connected to the drain contact region of the active layer of the first thin film transistor through a through hole.