Abstract: A processor architecture utilizing a L3 translation lookaside buffer (TLB) to reduce page walks. The processor includes multiple cores, where each core includes a L1 TLB and a L2 TLB. The processor further includes a L3 TLB that is shared across the processor cores, where the L3 TLB is implemented in off-chip or die-stack dynamic random-access memory. Furthermore, the processor includes a page table connected to the L3 TLB, where the page table stores a mapping between virtual addresses and physical addresses. In such an architecture, by having the L3 TLB with a very large capacity, performance may be improved, such as execution time, by eliminating page walks, which requires multiple data accesses.

Abstract: A processor architecture which partitions on-chip data caches to efficiently cache translation entries alongside data which reduces conflicts between virtual to physical address translation and data accesses. The architecture includes processor cores that include a first level translation lookaside buffer (TLB) and a second level TLB located either internally within each processor core or shared across the processor cores. Furthermore, the architecture includes a second level data cache (e.g., located either internally within each processor core or shared across the processor cores) partitioned to store both data and translation entries. Furthermore, the architecture includes a third level data cache connected to the processor cores, where the third level data cache is partitioned to store both data and translation entries. The third level data cache is shared across the processor cores. The processor architecture can also include a data stack distance profiler and a translation stack distance profiler.

Abstract: A processor architecture which partitions the on-chip data caches to efficiently cache translation entries alongside data which reduces the conflicts between virtual to physical address translation and data accesses. The architecture includes processor cores that include a first level translation lookaside buffer (TLB) and a second level TLB located either internally within each processor core or shared across the processor cores. Furthermore, the architecture includes a second level data cache (e.g., located either internally within each processor core or shared across the processor cores) partitioned to store both data and translation entries. Furthermore, the architecture includes a third level data cache connected to the processor cores, where the third level data cache is partitioned to store both data and translation entries. The third level data cache is shared across the processor cores.

Abstract: A processor architecture utilizing a L3 translation lookaside buffer (TLB) to reduce page walks. The processor includes multiple cores, where each core includes a L1 TLB and a L2 TLB. The processor further includes a L3 TLB that is shared across the processor cores, where the L3 TLB is implemented in off-chip or die-stack dynamic random-access memory. Furthermore, the processor includes a page table connected to the L3 TLB, where the page table stores a mapping between virtual addresses and physical addresses. In such an architecture, by having the L3 TLB with a very large capacity, performance may be improved, such as execution time, by eliminating page walks, which requires multiple data accesses.

Abstract: Provided are a method and apparatus for increasing task-execution speed, and, more particularly, a method and apparatus for increasing task-execution speed by compiling code to bytecodes, and executing native code in units of blocks instead of bytecodes, in which a block is a group of a series of bytecodes. The apparatus includes a receiving unit which receives a bytecode, a control unit which identifies whether the received bytecode is the last bytecode of a block, and a transmitting unit which transmits an address of a first native code of one or more native codes that correspond to one or more bytecodes included in the block based on the identification result.

Abstract: An apparatus and method for accelerating Java translation are provided. The apparatus includes a lookup table which stores an lookup table having arrangements of bytecodes and native codes corresponding to the bytecodes, a decoder which generates pointer to the native code corresponding to the feed bytecode in the lookup table, a parameterized bytecode processing unit which detects parameterized bytecode among the feed bytecode, and generating pointer to native code required for constant embedding in the lookup table, a constant embedding unit which embeds constants into the native code with the pointer generated by the parameterized bytecode processing unit, and a native code buffer which stores the native code generated by the decoder or the constant embedding unit.

Abstract: The proposed method exploits inherent characteristics of a software program to select a core of a multi-core processor for executing the software program. Each characteristic is associated with a suitability metric, which measures the degree of the match between that characteristic and the corresponding hardware configuration. In one embodiment, fuzzy logic is used to combine individual metrics to produce an overall suitability that indicates the overall degree of the match between a program and a core.

Abstract: An apparatus and method for accelerating Java translation are provided. The apparatus includes a lookup table which stores an lookup table having arrangements of bytecodes and native codes corresponding to the bytecodes, a decoder which generates pointer to the native code corresponding to the feed bytecode in the lookup table, a parameterized bytecode processing unit which detects parameterized bytecode among the feed bytecode, and generating pointer to native code required for constant embedding in the lookup table, a constant embedding unit which embeds constants into the native code with the pointer generated by the parameterized bytecode processing unit, and a native code buffer which stores the native code generated by the decoder or the constant embedding unit.

Abstract: A method and apparatus for an instantly-on computer system is presented. A computer that incorporates fast non-volatile primary memory for storing the operating system, resulting in an instant-on or instant-booting of the computer. Large parts of the operating system code and application code are stored in non-volatile write-protectable areas that cannot be modified by malicious sources, resulting in a secure computer. It solves the problem from typical computers having to load the operating system and applications from a slow device such as the hard disk to the main memory. This loading is avoided by permanently housing the operating system in a non-volatile main memory. The system also solves the problem of corruption of operating system areas from malicious sources. The memory contains writeable and write-protected areas and a memory controller controls the access to the various regions of the memory.

Abstract: An apparatus and method for accelerating Java translation are provided. The apparatus includes a lookup table which stores an lookup table having arrangements of bytecodes and native codes corresponding to the bytecodes, a decoder which generates pointer to the native code corresponding to the feed bytecode in the lookup table, a parameterized bytecode processing unit which detects parameterized bytecode among the feed bytecode, and generating pointer to native code required for constant embedding in the lookup table, a constant embedding unit which embeds constants into the native code with the pointer generated by the parameterized bytecode processing unit, and a native code buffer which stores the native code generated by the decoder or the constant embedding unit.

Abstract: A method and apparatus for instantly-available applications in a computer system is presented. A computer that incorporates fast non-volatile primary memory for storing the application software and/or operating system, resulting in an instant-on computer is presented. Large parts of the application code and/or operating system code are stored in non-volatile write-protectable areas of the memory that cannot be modified by malicious sources, resulting in a secure computer. It solves the problem of typical computers having to load the applications from a slow device such as the hard disk to the main memory. This loading is avoided by permanently housing the applications in a non-volatile main memory. The system also solves the problem of corruption of application software areas from malicious sources. The memory system contains writeable and write-protected areas and a memory controller that controls the access to the various regions of the memory.

Abstract: An apparatus and a system, as well as a method and article, may operate to predict a branch within a first operating context, such as a user context, using a first strategy; and to predict a branch within a second operating context, such as an operating system context, using a second strategy. In some embodiments, apparatus and systems may comprise one or more first storage locations to store branch history information associated with a first operating context, and one ore more second storage locations to store branch history information associated with a second operating context.

Abstract: A method and apparatus for instantly-available applications in a computer system is presented. A computer that incorporates fast non-volatile primary memory for storing the application software and/or operating system, resulting in an instant-on computer is presented. Large parts of the application code and/or operating system code are stored in non-volatile write-protectable areas of the memory that cannot be modified by malicious sources, resulting in a secure computer. It solves the problem of typical computers having to load the applications from a slow device such as the hard disk to the main memory. This loading is avoided by permanently housing the applications in a non-volatile main memory. The system also solves the problem of corruption of application software areas from malicious sources. The memory system contains writeable and write-protected areas and a memory controller that controls the access to the various regions of the memory.

Abstract: An apparatus and method for accelerating Java translation are provided. The apparatus includes a lookup table which stores an lookup table having arrangements of bytecodes and native codes corresponding to the bytecodes, a decoder which generates pointer to the native code corresponding to the feed bytecode in the lookup table, a parameterized bytecode processing unit which detects parameterized bytecode among the feed bytecode, and generating pointer to native code required for constant embedding in the lookup table, a constant embedding unit which embeds constants into the native code with the pointer generated by the parameterized bytecode processing unit, and a native code buffer which stores the native code generated by the decoder or the constant embedding unit.

Abstract: Provided are a method and apparatus for increasing task-execution speed, and, more particularly, a method and apparatus for increasing task-execution speed by compiling code to bytecodes, and executing native code in units of blocks instead of bytecodes, in which a block is a group of a series of bytecodes. The apparatus includes a receiving unit which receives a bytecode, a control unit which identifies whether the received bytecode is the last bytecode of a block, and a transmitting unit which transmits an address of a first native code of one or more native codes that correspond to one or more bytecodes included in the block based on the identification result.

Abstract: An apparatus and a system, as well as a method and article, may operate to predict a branch within a first operating context, such as a user context, using a first strategy; and to predict a branch within a second operating context, such as an operating system context, using a second strategy. In some embodiments, apparatus and systems may comprise one or more first storage locations to store branch history information associated with a first operating context, and one ore more second storage locations to store branch history information associated with a second operating context.

Abstract: An apparatus and a system, as well as a method and article, may operate to predict a branch within a first operating context, such as a user context, using a first strategy; and to predict a branch within a second operating context, such as an operating system context, using a second strategy. In some embodiments, apparatus and systems may comprise one or more first storage locations to store branch history information associated with a first operating context, and one ore more second storage locations to store branch history information associated with a second operating context.