Abstract: A fault detecting multi-thread pipeline processor with fault detection is operative with a single pipeline stage which generates branch status comprising at least one of branch taken/not_taken, branch direction, and branch target. A first thread has control and data instructions, the control instructions comprising loop instructions including unconditional and conditional branch instructions, loop initialization instructions, loop arithmetic instructions, and no operation (NOP) instructions. A second thread has only control instructions and either has the non-control instructions replaced with NOP instructions, or removed entirely. A fault detector compares the branch status of the first thread and second thread and asserts a fault output when they do not match.

Abstract: A programmable address generator has an iteration variable generator for generation of an ordered set of iteration variables, which are re-ordered by an iteration variable selection fabric, which delivers the re-ordered iteration variables to one or more address generators. A configurator receives an instruction containing fields which provide configuration constants to the address generator, iteration variable selection fabric, and address generators. After configuration, the address generators provide addresses coupled to a memory. In one example of the invention, the address generators generate an input address, a coefficient address, and an output address for performing convolutional neural network inferences.

Abstract: A process for iterating through a multi-dimensional array has an iteration process and an address generation process. In one example of the invention an input address process, a coefficient address process, and an output address process generate addresses for a convolutional neural network (CNN. Each of the input address process, coefficient address process, and output address process is coupled to a plurality of iteration variables generated by an iteration variable process, each iteration variable process having an associated with a bound and stride for each iteration variable, thereby generating an input address, a coefficient address, and an output address.

Abstract: A programmable address generator has an iteration variable generator for generation of an ordered set of iteration variables, which are re-ordered by an iteration variable selection fabric, which delivers the re-ordered iteration variables to one or more address generators. A configurator receives an instruction containing fields which provide configuration constants to the address generator, iteration variable selection fabric, and address generators. After configuration, the address generators provide addresses coupled to a memory. In one example of the invention, the address generators generate an input address, a coefficient address, and an output address for performing convolutional neural network inferences.

Abstract: A secure processor with fault detection has a core thread which executes with a redundant branch processor thread. In one configuration, the core thread is operative on a fully functional core processor configured to execute a complete instruction set, and the redundant branch processor thread contains only initialization instructions and flow control instructions such as branch instructions and is operative on a redundant branch processor which is configured to execute a subset of the complete instruction set, specifically a branch control variable initialization and a branch instruction, thereby greatly simplifying the redundant branch processor architecture. Fault conditions are detected by comparing either a history of branch taken/not taken and branch targets, or a comparison of program counter activity for the core thread and redundant branch processor thread.

Abstract: A fault detecting multi-thread pipeline processor with fault detection is operative with a single pipeline stage which generates branch status comprising at least one of branch taken/not_taken, branch direction, and branch target. A first thread has control and data instructions, the control instructions comprising loop instructions including unconditional and conditional branch instructions, loop initialization instructions, loop arithmetic instructions, and no operation (NOP) instructions. A second thread has only control instructions and either has the non-control instructions replaced with NOP instructions, or removed entirely. A fault detector compares the branch status of the first thread and second thread and asserts a fault output when they do not match.

Abstract: Systems and methods for a new field programmable gate array (FPGA) architecture that is optimized for machine learning (ML) applications are provided. Such ML applications can specifically include, for example, artificial neural networks and deep neural networks. Various embodiments enable the design of faster and more power efficient hardware accelerators for machine learning algorithms, compared to existing FPGAs in the market. This is made possible by hard systolic matrix multiplier blocks, hard activation blocks and soft ML-centric configurable logic blocks. The matrix multiplier blocks are connected to field programmable interconnect resources to enable creation of larger matrix multipliers. The hard matrix multipliers and the hard activation blocks have programmable interconnects between them and neighboring memory or compute blocks on the device.

Abstract: A method, system and computer program product for generating sets of training programs for machine learning models. Fixed values of one or more workload metrics are received from a user, where the workload metrics correspond to low-level program features which define particular low-level application behavior. A profile using the fixed values of the workload metrics is then created. A suite of synthetic applications is generated using the created profile to form a set of training programs which target particular aspects of program behavior. A machine learning model is then trained using the set of training programs. Since the generated synthetic applications provide a broader coverage of the program state-space, the formed set of training programs more accurately targets performance behavior thereby improving the prediction accuracy of the machine learning based predictive models.

Abstract: A method, system and computer program product for load balancing of graph processing workloads. Synthetic proxy graphs are generated to characterize machines' graph processing speeds in a cluster. Each of the graph applications executing in the cluster is profiled using the synthetic graphs to form profiling sets. These formed profiling sets are run among the machines in the cluster to capture the machines' graph processing speeds. A metric for each of the graph applications is computed from a relative speedup among the machines in the cluster and/or the graph processing speeds. A graph file of a natural graph and a graph application are loaded. A metric out of the computed metrics is selected based on the graph application. The natural graph is then partitioned into multiple chunks which is distributed onto two or more machines in the cluster based on the selected metric and a user selected partitioning algorithm.

Abstract: A method, system and computer program product for generating sets of training programs for machine learning models. Fixed values of one or more workload metrics are received from a user, where the workload metrics correspond to low-level program features which define particular low-level application behavior. A profile using the fixed values of the workload metrics is then created. A suite of synthetic applications is generated using the created profile to form a set of training programs which target particular aspects of program behavior. A machine learning model is then trained using the set of training programs. Since the generated synthetic applications provide a broader coverage of the program state-space, the formed set of training programs more accurately targets performance behavior thereby improving the prediction accuracy of the machine learning based predictive models.

Abstract: A method, system and computer program product for load balancing of graph processing workloads. Synthetic proxy graphs are generated to characterize machines' graph processing speeds in a cluster. Each of the graph applications executing in the cluster is profiled using the synthetic graphs to form profiling sets. These formed profiling sets are run among the machines in the cluster to capture the machines' graph processing speeds. A metric for each of the graph applications is computed from a relative speedup among the machines in the cluster and/or the graph processing speeds. A graph file of a natural graph and a graph application are loaded. A metric out of the computed metrics is selected based on the graph application. The natural graph is then partitioned into multiple chunks which is distributed onto two or more machines in the cluster based on the selected metric and a user selected partitioning algorithm.

Abstract: The present invention discloses a convenient method for easily disconnecting and connecting internet to/from a computer. Instead of plugging and unplugging the physical cable that connects to the internet, a facility is invented to conveniently connect and disconnect internet using a switch on an internet cable or a convenient switch on the keyboard or monitor/display or the computer housing/box itself. Instead of pressing a switch, a key or swipe card can be used to activate the switch. Alternately the internet connection can be activated by opening a browser. The invention can be integrated into the browser to disable the internet connection during periods of inactivity. The key or swipe card can additionally be used to implement access restrictions, for instance controlling hours of access or disallowed sites for a child.

Abstract: The present invention provides a system, method and apparatus for allocating resources by assigning resource identifiers to processor resources using at least a portion of a pseudorandom sequence. One or more resource identifiers are generated using at least a portion of each a pseudorandom sequence. Each resource identifier corresponds to one of the resources. One or more of the resource identifiers are then selected for allocation to the instruction.

Abstract: The present invention provides a system, method and apparatus for allocating resources by assigning resource identifiers to processor resources using at least a portion of a pseudorandom sequence. One or more resource identifiers are generated using at least a portion of each a pseudorandom sequence. Each resource identifier corresponds to one of the resources. One or more of the resource identifiers are then selected for allocation to the instruction.

Abstract: A programmable memory circuit including the facility to reconfigure it's format