Patents by Inventor Ljubisa Bajic

Ljubisa Bajic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8650428
    Abstract: A system includes a power management unit that may be configured to estimate the power consumed by at least a portion of each of one or more processor cores during operation of each processor core. The power management unit may be configured to generate a sum of activity values and normal weight factor values for a predetermined set of signals within each processor core to estimate the power consumed. The power management unit may also be configured to adaptively generate and selectively use new weight factor values to estimate the power consumed based upon a total measured dynamic power consumed by each processor core during operation.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: February 11, 2014
    Assignee: ATI Technologies ULC
    Inventors: Lejla Bajic, Ljubisa Bajic
  • Publication number: 20130275778
    Abstract: A power controller can set the power state of a processor bridge based on which processor modules are in a communicative state. In addition, for a power state where selected processor modules are expected to be non-communicative, the power controller can set the supplied voltage to have a reduced voltage guard band as compared to other power states. These power management techniques can reduce the power consumed by the processor.
    Type: Application
    Filed: April 13, 2012
    Publication date: October 17, 2013
    Applicants: ATI TECHNOLOGIES ULC, ADVANCED MICRO DEVICES, INC.
    Inventors: Maurice B. Steinman, Alexander J. Branover, Denis J. Foley, Ljubisa Bajic
  • Publication number: 20130159755
    Abstract: A method and apparatus includes a multi-processor apparatus including a plurality of integrated circuit processors having a shared thermal platform. Each processor has at least one subsystem operable at a plurality of different power settings, at least one internal thermal parameter detector providing power data related to the processor, and a power management unit. The method and apparatus illustratively shares power data from the at least one internal thermal parameter detector of each processor between the power management units of the plurality of processors; compares the shared power data from the plurality of processors to a thermal design power limit for the shared thermal platform; and controls a power setting of the at least one subsystem of the plurality of processors within the shared thermal platform based on the comparison of the shared power data to the thermal design power limit for the shared thermal platform.
    Type: Application
    Filed: December 19, 2011
    Publication date: June 20, 2013
    Applicants: Advanced Micro Devices, Inc., ATI Technologies, ULC
    Inventors: Stephen D. Presant, Alexander J. Branover, Oleksandr Khodorkovsky, Ljubisa Bajic
  • Publication number: 20130024713
    Abstract: A system includes a power management unit that may be configured to estimate the power consumed by at least a portion of each of one or more processor cores during operation of each processor core. The power management unit may be configured to generate a sum of activity values and normal weight factor values for a predetermined set of signals within each processor core to estimate the power consumed. The power management unit may also be configured to adaptively generate and selectively use new weight factor values to estimate the power consumed based upon a total measured dynamic power consumed by each processor core during operation.
    Type: Application
    Filed: July 19, 2011
    Publication date: January 24, 2013
    Inventors: Lejla Bajic, Ljubisa Bajic
  • Patent number: 8102398
    Abstract: A graphics processor may be operated in a reduced power mode to render frames at rate equal to or less than the rate at which frames are presented on an interconnected display. Graphics processor clock speeds are controlled to reduce the time during which the graphics processor is idle between rendering frames. The graphics processor clock speed may thus be slowed without impacting the quality of rendered images. At the same time the voltage applied to power the graphics processor may be reduced. Optionally, a back bias voltage may further be applied to the processor substrate to reduce power consumption. Clock speed and voltage levels may be adjusted using closed-loop control.
    Type: Grant
    Filed: March 3, 2006
    Date of Patent: January 24, 2012
    Assignee: ATI Technologies ULC
    Inventors: Ljubisa Bajic, James Fry
  • Publication number: 20070206018
    Abstract: A graphics processor may be operated in a reduced power mode to render frames at rate equal to or less than the rate at which frames are presented on an interconnected display. Graphics processor clock speeds are controlled to reduce the time during which the graphics processor is idle between rendering frames. The graphics processor clock speed may thus be slowed without impacting the quality of rendered images. At the same time the voltage applied to power the graphics processor may be reduced. Optionally, a back bias voltage may further be applied to the processor substrate to reduce power consumption. Clock speed and voltage levels may be adjusted using closed-loop control.
    Type: Application
    Filed: March 3, 2006
    Publication date: September 6, 2007
    Inventors: Ljubisa Bajic, James Fry