Abstract: A transistor device having a channel region including a portion located in a sidewall of semiconductor material of a trench and an extended drain region including a portion located in a lower portion of the semiconductor material of the trench. In one embodiment, a control terminal of the transistor device is formed by patterning a layer of control terminal material to form a sidewall in the trench and a field plate for the transistor device is formed by forming a conductive sidewall spacer structure along the sidewall of the control terminal material.

Abstract: A transistor includes a trench formed in a semiconductor substrate with the trench having a first sidewall and a second sidewall. A gate region includes a conductive material filled in the trench. A drift region having a first conductivity type is formed in the semiconductor substrate adjacent to the second sidewall. A drain region is formed in the drift region and separated from the second sidewall by a first distance. A dielectric layer is formed at the top surface of the semiconductor substrate covering the gate region and the drift region between the second sidewall and the drain region. A field plate is formed over the dielectric layer and isolated from the conductive material and the drift region by way of the dielectric layer.

Abstract: Disclosed herein is a transistor structure that is formed by forming a sidewall spacer along a first vertical component sidewall of a trench wherein no sidewall spacer is formed along a second vertical component sidewall of the trench. During an etching of a dielectric layer in the trench, the sidewall spacer protects a first portion of the dielectric layer from being etched while a second portion of the dielectric layer along the second sidewall is etched. A portion of a control terminal can be formed in the space where the second portion is removed.

Abstract: A semiconductor device includes a semiconductor substrate with a collector region formed within the semiconductor substrate. A base region, including a first base region and a second base region, is formed over the collector region. An extrinsic base region is formed laterally adjacent to and coupled to the second base region. A base link region is disposed proximate to the second base region, wherein the base link region couples the extrinsic base sidewall to the second base region. A method for forming a semiconductor device includes forming the collector region within the semiconductor substrate, forming a plurality of dielectric layers over the collector region, forming an extrinsic base layer over the collector region, etching an emitter window, forming the first base region over the collector region, forming the second base region over the first base region, wherein forming the second base region includes forming the base link region.

Abstract: A transistor device includes a substrate, a first current-carrying region having a first lateral width, and a second current-carrying region. A first trench is formed between the first current-carrying region and the second current-carrying region. The first trench includes a first vertical component sidewall coupled to the first current-carrying region and a second vertical component sidewall coupled to the second current-carrying region. A first termination region includes a first termination portion coupled to the first current-carrying region, a second termination portion coupled to the second current-carrying region, and a first trench termination portion coupled to the first trench. The first trench and the first trench termination portion surround a portion of the first current-carrying region, and the second current-carrying region and the second termination portion surrounds a portion of the first trench and the first trench termination portion.

Abstract: A method of forming a transistor device where an extended drain region is formed by performing angled ion implantation of conductivity dopants of a first conductivity type into the sidewalls and bottom portion of a trench. The bottom portion of the trench is then implanted with dopants of a second conductivity type. Source and drain regions are formed on opposing sides of the trench including in upper portions of the trench sidewalls. A channel region is formed in a trench sidewall below the source region. The trench includes a control terminal structure. After formation of the transistor device, the net conductivity type of the bottom portion of the trench is of the first conductivity type.

Abstract: Disclosed herein is a conductive structure that serves as both a control terminal and a field plate for a transistor. The transistor includes a channel region including a portion located in a vertical sidewall of semiconductor material that separates an upper level portion and a lower level portion of the semiconductor material. An extended drain region includes a portion located in the lower portion of the semiconductor material. The conductive structure is laterally adjacent to the vertical sidewall and includes a first vertical side and an opposite second vertical side with the first vertical side being closer to the vertical component sidewall. The first side is vertically closer to the lower level portion of the semiconductor material than the second vertical side.

Abstract: A transistor device includes a channel region including a portion located in a vertical sidewall of semiconductor material and an extended drain region including a portion located in a lower portion of the semiconductor material. In one embodiment, a control terminal of the transistor device is formed by forming a conductive sidewall spacer structure adjacent to the sidewall and a field plate for the transistor device is formed by forming a second conductive sidewall spacer structure.

Abstract: Disclosed herein is a conductive structure that serves as both a control terminal and a field plate for a transistor. The transistor includes a channel region including a portion located in a vertical sidewall of semiconductor material that separates an upper level portion and a lower level portion of the semiconductor material. An extended drain region includes a portion located in the lower portion of the semiconductor material. The conductive structure is laterally adjacent to the vertical sidewall and includes a first vertical side and an opposite second vertical side with the first vertical side being closer to the vertical component sidewall. The first side is vertically closer to the lower level portion of the semiconductor material than the second vertical side.

Abstract: A transistor device includes a channel region including a portion located in a vertical sidewall of semiconductor material and an extended drain region including a portion located in a lower portion of the semiconductor material. In one embodiment, a control terminal of the transistor device is formed by forming a conductive sidewall spacer structure adjacent to the sidewall and a field plate for the transistor device is formed by forming a second conductive sidewall spacer structure.

Abstract: A method of forming a transistor device where an extended drain region is formed by performing angled ion implantation of conductivity dopants of a first conductivity type into the sidewalls and bottom portion of a trench. The bottom portion of the trench is then implanted with dopants of a second conductivity type. Source and drain regions are formed on opposing sides of the trench including in upper portions of the trench sidewalls. A channel region is formed in a trench sidewall below the source region. The trench includes a control terminal structure. After formation of the transistor device, the net conductivity type of the bottom portion of the trench is of the first conductivity type.

Abstract: A continuous buried doped isolation region in a substrate of a die. The substrate includes an isolation ring structure surrounding a first area of the die. The continuous buried doped isolation region is of a net first conductivity type and is located in the first area. The continuous buried doped isolation region including a first portion having a net first conductivity type dopant concentration of at least a first level located in an interior region of the first area and extending to a sidewall of the isolation ring structure. The first portion does not extend to the sidewall of the isolation ring structure in a location of a corner area of the first area. The corner area is defined by the isolation ring structure. A second portion of the continuous buried doped isolation region in the corner area has a net first conductivity type dopant concentration of a second level that is lower than the first level.

Abstract: A transistor device includes a conductive structure located in a trench of semiconductor material. The conductive structure is located closer to a first sidewall of the trench than to a second sidewall of the trench. The conductive structure serves as a control terminal and a field plate for a transistor. At a first location in the trench where the conductive structure functions as a control terminal for a transistor, the conductive structure is located a first lateral distance from the trench sidewall with dielectric located in between. At a second location in the trench where the conductive structure functions as a field plate, the conductive structure is located a second lateral distance from the trench sidewall with dielectric located in between. The second lateral distance is greater than the first lateral distance.

Abstract: A trench structure is located directly laterally between a first well and a first source region for a first transistor and the second well region with a second source for a second transistor. The trench structure includes a first gate structure for the first transistor, a second gate structure for the second transistor, a first conductive field plate structure, and a second conductive field plate structure. The first gate structure, the first field plate structure, the second field plate structure, and the second gate structure are located in the trench structure in a lateral line between the first well region and the second well region. The trench structure includes a dielectric separating the first field plate structure and the second field plate structure from each other in the lateral line. A drain region for the first transistor and the second transistor includes a portion located directly below the trench structure.

Abstract: A transistor includes a trench formed in a semiconductor substrate. A gate electrode is formed in the trench with a first edge of the gate electrode proximate to a first sidewall of the trench. A first field plate is formed in the trench with the first field plate located between a second edge of the gate electrode and a second sidewall of the trench. A dielectric material is formed in the trench with the dielectric material having a first thickness between the first sidewall and a first edge of the first field plate, and a second thickness between the second sidewall and a second edge of the first field plate, the second thickness larger than the first thickness.

Abstract: A continuous buried doped isolation region in a substrate of a die. The substrate includes an isolation ring structure surrounding a first area of the die. The continuous buried doped isolation region is of a net first conductivity type and is located in the first area. The continuous buried doped isolation region including a first portion having a net first conductivity type dopant concentration of at least a first level located in an interior region of the first area and extending to a sidewall of the isolation ring structure. The first portion does not extend to the sidewall of the isolation ring structure in a location of a corner area of the first area. The corner area is defined by the isolation ring structure. A second portion of the continuous buried doped isolation region in the corner area has a net first conductivity type dopant concentration of a second level that is lower than the first level.

Abstract: A transistor includes a trench formed in a semiconductor substrate with the trench having a first sidewall and a second sidewall. A vertical field plate is formed in the trench and the vertical field plate is located between the first sidewall and the second sidewall. A gate electrode is formed in the trench with a first edge of the gate electrode proximate to the first sidewall and a second edge of the gate electrode proximate to the vertical field plate. A first dielectric material is formed in the trench between the first sidewall and the vertical field plate. A second dielectric material is formed in the trench between the vertical field plate and the second sidewall with the second dielectric material having a dielectric constant lower than that of the first dielectric material.

Abstract: Disclosed is a power device, such as power MOSFET, and method for fabricating same. The device includes an upper trench situated over a lower trench, where the upper trench is wider than the lower trench. The device further includes a trench dielectric inside the lower trench and on sidewalls of the upper trench. The device also includes an electrode situated within the trench dielectric. The trench dielectric of the device has a bottom thickness that is greater than a sidewall thickness.

Abstract: A plurality of trench stripes are disposed in parallel in an epitaxial layer on a drain and extends from a top region to a bottom region of a first surface of the semiconductor. A first polysilicon layer is in each of the trench stripes. The first polysilicon layer extends between the drain and the first surface proximal to the top region and the bottom region, and between the drain and a level below the first surface in a middle region between the top region and the bottom region. A second polysilicon layer is over the first polysilicon layer in the middle region, wherein the first poly silicon layer forms a shield, and the second polysilicon layer forms a gate. A source is in a silicon mesa stripe surrounding the first trench stripe.

Abstract: A transistor includes a trench formed in a semiconductor substrate with the trench having a first sidewall and a second sidewall. A vertical field plate is formed in the trench. The vertical field plate is located between the first sidewall and the second sidewall. A gate electrode is formed in the trench with a first edge of the gate electrode proximate to the first sidewall and a second edge of the gate electrode proximate to the vertical field plate. A dielectric material is formed in the trench between the first sidewall and the vertical field plate. An air cavity is formed in the trench between the vertical field plate and the second sidewall with the air cavity having a dielectric constant lower than that of the dielectric material.