Abstract: A signal conditioning circuit for a light sensor, in particular for an ambient light sensor, comprises a first integration stage (INT1) connected to a first sensor input (IN1) to receive a first and second sensor signal and a second integration stage (INT2) comprising a coupling input (IN2) to receive from the first integration stage (INT1) a first and second integrated sensor signal. A coupling stage (S3, C5) is connecting the first and second integration stages (INT1, INT2) and is designed to generate a difference signal from consecutively received integrated first and second integrated sensor signals. A sensor arrangement and a method for signal conditioning for a light sensor is also presented.

Abstract: A light sensor arrangement according to the proposed principle comprises at least one first unshielded well (D0) and at least one second shielded well (D1) in a substrate (P). The at least one first unshielded well (D0) is being exposed to incident light (?) and configured to generate a first sensor signal (Ch0) as a function of the incident light (?). The at least one second shielded well (D1) in the substrate (p) being shielded from the incident light (?) and configured to generate a second sensor signal (Ch1) as a function of the incident light (?). The light sensor arrangement further comprises means for temperature compensation providing the first and second sensor signals (Ch0, Ch1) as temperature compensated sensor signals as a function of substrate temperature. Means to determine spectral content of the incident light (?) are provided to determine the spectral content as a function of the temperature compensated first and second sensor signals (Ch0, Ch1).

Abstract: A signal conditioning circuit for a light sensor, in particular for an ambient light sensor, comprises a first integration stage (INT1) connected to a first sensor input (IN1) to receive a first and second sensor signal and a second integration stage (INT2) comprising a coupling input (IN2) to receive from the first integration stage (INT1) a first and second integrated sensor signal. A coupling stage (S3, C5) is connecting the first and second integration stages (INT1, INT2) and is designed to generate a difference signal from consecutively received integrated first and second integrated sensor signals. A sensor arrangement and a method for signal conditioning for a light sensor is also presented.

Abstract: A light sensor arrangement according to the proposed principle comprises at least one first unshielded well (D0) and at least one second shielded well (D1) in a substrate (P). The at least one first unshielded well (D0) is being exposed to incident light (?) and configured to generate a first sensor signal (Ch0) as a function of the incident light (?). The at least one second shielded well (D1) in the substrate (p) being shielded from the incident light (?) and configured to generate a second sensor signal (Ch1) as a function of the incident light (?). The light sensor arrangement further comprises means for temperature compensation providing the first and second sensor signals (Ch0, Ch1) as temperature compensated sensor signals as a function of substrate temperature. Means to determine spectral content of the incident light (?) are provided to determine the spectral content as a function of the temperature compensated first and second sensor signals (Ch0, Ch1).

Abstract: A single shared processing path is used as contexts are switched during processing. Each unique context is processed using a corresponding unique pipeline. If a pipeline that is executing under one context stalls, processing is switched in the shared processing path to another pipeline that is executing under second context. New pipelines are enabled for execution by borrowing a clock cycle from the currently executing pipeline. In some cases contexts are assigned various relative priority levels. In one case a context switching microprocessor is used in a communication engine portion of a system-on-a-chip communication system.

Abstract: A single shared processing path is used as contexts are switched during processing. Each unique context is processed using a corresponding unique pipeline. If a pipeline that is executing under one context stalls, processing is switched in the shared processing path to another pipeline that is executing under second context. New pipelines are enabled for execution by borrowing a clock cycle from the currently executing pipeline. In some cases contexts are assigned various relative priority levels. In one case a context switching microprocessor is used in a communication engine portion of a system-on-a-chip communication system.

Abstract: Data processing system (800) and process (100) produce a hierarchical interconnection description of an integrated circuit design from a plurality of functional modules and a desired hierarchy. After an integrated circuit description is received (102), an interconnection structure is created (104) for each hierarchical level and functional module within the integrated circuit description. Based upon the desired hierarchy, a hierarchical tree is generated. Based upon the hierarchical tree, the interconnection structures are filled (106) with relevant interconnection and pin information to define interconnections among functional modules and hierarchical levels. After each interconnection structure is filled, a complete hierarchical interconnection description of the integrated circuit design has been completed. Finally, the hierarchical interconnection description is output (108).

Abstract: A fiber data distributed interface (FDDI) system uses an MLT3A encoding scheme in order to reduce DC bias or baseline wander. The MLT3A encoding scheme is a scheme wherein logical zeros are transmitted as ground voltages and logical ones are transmitted as one of either positive voltages or negative voltages depending upon past transmission history (FIG. 4 ) wherein the past history is recorded by a counter C or an analog circuit. MLT3A ensures that the baseline wander or DC bias returns to zero or is maintained as close to zero as possible in a timely manner so that no FDDI systems will fail from baseline wander.

Abstract: An integrated circuit for use in fiber distributed data interface (FDDI) system has four elastic layer and buffer management (ELM) circuits (12, 14, 16, and 18) coupled through a crossbar switch (20). The crossbar switch (20) allows any of the ELM circuits (12, 14, 16, and 18) to be coupled to any other ELM circuit (12, 14, 16, or 18) or to one of three external buses for FDDI communication. By using a crossbar switch and four ELM devices on a single integrated circuit, FDDI performance is improved while system design is made easier and more flexible than previously possible. Cipher circuitry (22, 24, 26, and 28) is used to scramble and descramble data ingoing and outcoming from the ELM devices. Concentrators, workstations, local area networks (LANs), and the like may incorporate the circuit (10) to improve performance and flexibility.

Abstract: An integrated circuit for use in fiber data distributed interface (FDDI) system has four elastic layer and buffer management (ELM) circuits (12, 14, 16, and 18) coupled through a crossbar switch (20). The crossbar switch (20) allows any of the ELM circuits (12, 14, 16, and 18) to be coupled to any other ELM circuit (12, 14, 16, or 18) or to one of three external buses for FDDI communication. By using a crossbar switch and four ELM devices on a single integrated circuit, FDDI performance is improved while system design is made easier and more flexible than previously possible. Cipher circuitry (22, 24, 26, and 28) is used to scramble and descramble data ingoing and outcoming from the ELM devices. Concentrators, workstations, local area networks (LANs), and the like may incorporate the circuit (10) to improve performance and flexibility.

Abstract: Arbitration is performed among a plurality of users for access to a shared resource in a system of the kind in which the users arbitrate by placing arbitration signals on a line and subsequently comparing their arbitration signals with a signal appearing on the line, by providing the users with independently operating clocks, and controlling the progression of the arbitration based on timing provided by the clock of at least one of the users. The progression of the arbitration thus does not depend upon a single master clock, or upon synchronizing the individual user clocks.

Abstract: A packet switching system is disclosed for transmitting variable length packets between system ports. Each byte of each packet has a special one-bit field for indicating whether the byte is the last byte of a packet. A "1" in this field specifies that the byte is the last byte of a packet and activates port control circuitry that changes the potential on a system control conductor to indicate that the system data bus is now idle and free for use by other ports.

Abstract: A clock recovery circuit for recovering the clock from an incoming data stream. The circuit comprises a transition detector and a module 3 counter operating at three times the expected rate of the incoming clock. A clock pulse is generated by the counter one count interval after a transition is detected.

Abstract: A packet switching system having separate arbitration and data buses together with circuitry for dividing the buses into a plurality of time segments termed phases. The plurality of phases permit a like plurality of separate arbitration operations and a like plurality of separate data exchanges to be effected concurrently on the arbitration bus and data bus, respectively. The use of n phases increases the data transmission capability of the system by a factor of n over prior art arrangements using only a single phase.

Abstract: A distributed packet switching system in which a centralized switch is not used and, instead, each transmitting port contains the intelligence required to derive and then insert the destination port and station addresses into the header of each packet to be transmitted by the port. The port circuitry that derives the destination addresses operates under control of a central controller which, prior to the setup of each call, receives information identifying the transmitting port and calling station as well as the destination station number dialed at the calling station. The controller processes this data to derive the destination port and station addresses. The derived addresses are sent to and stored in a RAM in the transmitting port. The RAM outputs the destination port and station addresses for each packet subsequently transmitted by the port on the call.