Abstract: A gang drilling machine for drilling a circuit card includes a pair of n and p master drills that are configured to be aligned in registry with respective n and p test vias of the card; pluralities of n and p minion drills that are configured to be aligned in registry with pluralities of n and p live vias of the card; and a controller that is electrically connected to control the n and p master drills and minion drills, and to send and receive electrical signals to and from the card. The controller is configured to: send a query signal to the card; monitor a response signal from the card; determine drilling depth of at least one of the master drills, in response to comparing the response signal to the query signal; and adjust operation of the machine, in response to the determined drilling depth.

Abstract: Embodiments are directed to a method of manufacturing the printed circuit board. The PCB is a multi-layer component, including a dielectric material and an intermediate or second layer adjacently positioned with respect to the dielectric material. The intermediate layer or second layer includes a conductor and fiberglass strands, with the fiberglass strands having an associated orientation. When assembled, the fiberglass and the conductor have a matching orientation and separation distance from a source to a destination.

Abstract: Embodiments are directed to a method of manufacturing the printed circuit board. The PCB is a multi-layer component, including a dielectric material and an intermediate or second layer adjacently positioned with respect to the dielectric material. The intermediate layer or second layer is comprised of a conductor and fiberglass strands, with the fiberglass strands having an associated orientation. When assembled, the fiberglass and the conductor having a matching orientation and separation distance from a source to a destination.

Abstract: Embodiments are directed to a printed circuit board and a method of manufacturing the printed circuit board. The PCB is a multi-layer component, including a dielectric material, an intermediate layer positioned adjacent to the dielectric material, and a conductor positioned adjacent to the intermediate layer. The intermediate layer is comprised of fiberglass strands having an associated orientation. When assembled, the fiberglass of the intermediate layer and the conductor having a matching orientation and separation distance from a source to a destination.

Abstract: A compact resistive thermal sensor is provided for an integrated circuit (IC), wherein different sensor components are placed on different layers of the IC. This allows the lateral area needed for the sensor resistance wire on any particular IC layer to be selectively reduced. In a useful embodiment, first linear conductive members are positioned in a first IC layer, in parallel relationship with one another. Second linear conductive members are positioned in a second IC layer in parallel relationship with one another. Conductive elements connect the first linear members into a first conductive path, and the second linear members into a second conductive path. A third conductive element extending between the first and second layers connects the first and second conductive paths into a single conductive path, wherein the path resistance varies with temperature. The path resistance is used to determine temperature.

Abstract: A compact resistive thermal sensor is provided for an integrated circuit (IC), wherein different sensor components are placed on different layers of the IC. This allows the lateral area needed for the sensor resistance wire on any particular IC layer to be selectively reduced. In a useful embodiment, a plurality of first linear conductive members are positioned in a first IC layer, in spaced-apart parallel relationship with one another. A plurality of second linear conductive members are similarly positioned in a second IC layer in spaced-apart parallel relationship with one another, and in orthogonal relationship with the first linear members or in parallel with existing wiring channels of the second IC layer. Conductive elements respectively connect the first linear members into a first conductive path, and the second linear members into a second conductive path.

Abstract: A compact resistive thermal sensor is provided for an integrated circuit (IC), wherein different sensor components are placed on different layers of the IC. This allows the lateral area needed for the sensor resistance wire on any particular IC layer to be selectively reduced. In a useful embodiment, a plurality of first linear conductive members are positioned in a first IC layer, in spaced-apart parallel relationship with one another. A plurality of second linear conductive members are similarly positioned in a second IC layer in spaced-apart parallel relationship with one another, and in orthogonal relationship with the first linear members or in parallel with existing wiring channels of the second IC layer. Conductive elements respectively connect the first linear members into a first conductive path, and the second linear members into a second conductive path.

Abstract: A compact resistive thermal sensor is provided for an integrated circuit (IC), wherein different sensor components are placed on different layers of the IC. This allows the lateral area needed for the sensor resistance wire on any particular IC layer to be selectively reduced. In a useful embodiment, a conductive element extending between first and second layers for connecting said first and second conductive paths into a single continuous conductive path having a resistance that varies with temperature. The sensor is responsive to electric current sent through said continuous path for determining temperature proximate to said continuous path from said path resistance.

Abstract: An encoding element (109, 111, 113) and a decoding arrangement (110, 112, 114) is included with each separate circuit (104, 105, 106) in a system (100) of circuits which must communicate digital signals with each other. The encoding devices (109, 111, 113) included with the separate circuits (104, 105, 106) cooperate to produce an encoded signal on a common transmission line or network (108) which interconnects the various circuits. The decoding arrangement (110, 112, 114) associated with each respective circuit receives the encoded signal appearing on the transmission line and decodes the encoded signal to reproduce or recreate the digital data signals transmitted from the other circuits in the system.

Abstract: Digital signals from a group of three or more circuits (104, 105, 106) are used to create an encoded or combined signal on a common transmission line (108). The encoded signal is then decoded at each different circuit to produce or recreate the digital signal asserted by each different circuit in the group. The encoded signal comprises a signal included in a set of unique signal values, with each signal in the set corresponding to a different combination of digital signals asserted by the group of circuits. Decoding the encoded signal at each circuit (104, 105, 106) in the group involves comparing the encoded signal to a particular reference voltage from a set of reference voltages. A particular reference voltage used in this comparison may be selected using one or more digital signals already decoded from the encoded signal.

Abstract: The present invention allows for the simultaneous transmission of two digital signals from one integrated circuit to another. The two digital signals are encoded utilizing a voltage divider circuit and are then transmitted by one transmission line to the second integrated circuit chip. The second integrated circuit chip decodes the first digital signal and then utilizes this decoded digital signal to further decode the second digital signal.

Abstract: The present invention allows for the simultaneous transmission of two digital signals from one integrated circuit to another. The two digital signals are encoded utilizing a voltage divider circuit and are then transmitted by one transmission line to the second integrated circuit chip. The second integrated circuit chip decodes the first digital signal and then utilizes this decoded digital signal to further decode the second digital signal.

Abstract: A driver circuit including of one or more fingers, or parallel driver circuits, senses for an overshoot or an undershoot condition of the signal transmitted onto a transmission line coupled to the driver circuit and compensates for such an overshoot or an undershoot by temporarily turning off the offending transition portion of the driver circuit, or finger portion. This is accomplished by turning off the transistor applying one of the two supply voltages coupled to the output transmission line. Effectively, the compensation circuitry within the driver circuit more closely matches the output impedance of the driver circuit to the impedance on the driven transmission line.

Abstract: A decoupling capacitor and protection circuit is provided that will assist the power supply network in stabilizing the voltage near circuits that demand short rapid transitions in electrical current. The protection circuit also significantly reduces the amount of electrical current drawn by defective large area decoupling capacitors. An inverter stage controls a switching circuit connected in series with a decoupling capacitor. A feedback circuit is provided from the output of the capacitor to the switching circuit. If the capacitor goes bad, then a voltage is present on the feedback circuit and the switching circuit ensures that the output of the failed capacitor is presented with an open circuit so that the short circuit current flow through the capacitor is eliminated. In this manner, the integrity of the other circuits located near the failed capacitor will operate appropriately.

Abstract: The present invention allows for the simultaneous transmission of three digital signals from one integrated circuit to another. The three digital signals are encoded utilizing series resistors of predetermined values and are then transmitted by one transmission line to the second integrated circuit chip. The second integrated circuit chip decodes the first digital signal and then utilizes this decoded first digital signal to further decode the second digital signal, and then utilizes the decoded first and second digital signals to decode the third digital signal.

Abstract: The present invention facilitates communication of signals from circuitry implemented with a first CMOS technology requiring a first voltage level supply for operation to circuitry implemented with a second CMOS technology requiring a second voltage level supply for operation, wherein the first and second voltage level supplies are not equal. The present invention receives from the circuitry implemented with a first CMOS technology a signal which has a first voltage level that is not acceptable for input into the circuitry implemented with a second CMOS technology. This signal is converted to a second voltage level that is acceptable for input into the circuitry implemented with a second CMOS technology, and then transmitted to the circuitry implemented with a second CMOS technology requiring a second voltage level supply for operation.