Abstract: A system includes a functional unit, at least one cache coupled to the functional unit, and a power management unit coupled to the functional unit and the at least one cache, the power management unit configured to trigger the functional unit to initiate prefetching of data to repopulate the at least one cache prior to a predicted exit of the functional unit from an idle mode to an active mode. The system further may include a prediction unit to predict the exit from the idle mode for the functional unit as occurring a predetermined duration from an entry into the idle mode. The prediction unit may determine the predetermined duration based on a history of idle mode durations indicative of durations of previous instances in which the functional unit was in the idle mode.

Abstract: A scheduler is presented that can adjust, responsive to a thermal condition at the processing device, a scheduling of process threads for compute units of the processing device so as to increase resource contentions between the process threads.

Abstract: A system includes a functional unit, at least one cache coupled to the functional unit, and a power management unit coupled to the functional unit and the at least one cache, the power management unit configured to trigger the functional unit to initiate prefetching of data to repopulate the at least one cache prior to a predicted exit of the functional unit from an idle mode to an active mode. The system further may include a prediction unit to predict the exit from the idle mode for the functional unit as occurring a predetermined duration from an entry into the idle mode. The prediction unit may determine the predetermined duration based on a history of idle mode durations indicative of durations of previous instances in which the functional unit was in the idle mode.

Abstract: A system and method are presented. Some embodiments include a processing unit, at least one memory coupled to the processing unit, and at least one cache coupled to the processing unit and divided into a series of blocks, wherein at least one of the series of cache blocks includes data identified as being in a modified state. The modified state data is flushed by writing the data to the at least one memory based on a write back policy and the aggressiveness of the policy is based on at least one factor including the number of idle cores, the proximity of the last cache flush, the activity of the thread associated with the data, and which cores are idle and if the idle core is associated with the data.

Abstract: A processor monitors, directly or indirectly, the amount of time it takes for the memory controller to respond to one or more memory access requests. When this memory access latency indicates that a memory latency tolerance of a program thread has been exceeded, the processor can apportion additional power to the memory controller, thereby increasing the speed with which the memory controller can process memory access requests.

Abstract: A scheduler is presented that can adjust, responsive to a thermal condition at the processing device, a scheduling of process threads for compute units of the processing device so as to increase resource contentions between the process threads.

Abstract: A processor includes a plurality of exclusive resources, a shared resource, and a controller configured to manage power state transitions of each of the plurality of exclusive resources and the shared resource. The controller receives a request from a resource to transition from a first power state to a lower power state and, in response to receiving the request, the controller controls power state transitions of the resource according to a first power control threshold when the resource is one of the plurality of exclusive resources and according to a second power control threshold that is greater than the first power control threshold when the resource is the shared resource.

Abstract: A system and method are presented. Some embodiments include a processing unit, at least one memory coupled to the processing unit, and at least one cache coupled to the processing unit and divided into a series of blocks, wherein at least one of the series of cache blocks includes data identified as being in a modified state. The modified state data is flushed by writing the data to the at least one memory based on a write back policy and the aggressiveness of the policy is based on at least one factor including the number of idle cores, the proximity of the last cache flush, the activity of the thread associated with the data, and which cores are idle and if the idle core is associated with the data.

Abstract: A processor includes a plurality of exclusive resources, a shared resource, and a controller configured to manage power state transitions of each of the plurality of exclusive resources and the shared resource. The controller receives a request from a resource to transition from a first power state to a lower power state and, in response to receiving the request, the controller controls power state transitions of the resource according to a first power control threshold when the resource is one of the plurality of exclusive resources and according to a second power control threshold that is greater than the first power control threshold when the resource is the shared resource.