Abstract: Various systems for managing chargeback, retrieval, and other requests from the card associations, issuing banks, merchant banks, or other financial institutions requiring a merchant's response are disclosed herein. Such systems may include various forms of hardware, software and manual processes intended to: (a) retrieve transaction requests; (b) retrieve merchant's transaction data; (c) gather merchant's data and compile with normalized transaction request data; (d) create response cases; (e) provide merchant notifications; and (f) transmit responses to requestors. With the present invention, these often independent and incompatible processes, including their non-standard data formats, are normalized and compiled into compatible formats that integrate and facilitate the automation of substantially all aspects of a given chargeback process in one embodiment.

Abstract: Various systems for managing chargeback, retrieval, and other requests from the card associations, issuing banks, merchant banks, or other financial institutions requiring a merchant's response are disclosed herein. Such systems may include various forms of hardware, software and manual processes intended to: (a) retrieve transaction requests; (b) retrieve merchant's transaction data; (c) gather merchant's data and compile with normalized transaction request data; (d) create response cases; (e) provide merchant notifications; and (f) transmit responses to requestors. With the present invention, these often independent and incompatible processes, including their non-standard data formats, are normalized and compiled into compatible formats that integrate and facilitate the automation of substantially all aspects of a given chargeback process in one embodiment.

Abstract: Bitcell layouts for use in electronic devices and systems are described. One embodiment relates to a memory including at least one bitcell, the bitcell including a storage cell region and a read channel region. The storage cell region is substantially L-shaped and includes six transistors. The read channel region is shaped to fit together with the substantially L-shaped storage cell region to form a substantially rectangular bitcell shape. Other embodiments are described and claimed.

Abstract: Bitcell layouts for use in electronic devices and systems are described. One embodiment relates to a memory including at least one bitcell, the bitcell including a storage cell region and a read channel region. The storage cell region is substantially L-shaped and includes six transistors. The read channel region is shaped to fit together with the substantially L-shaped storage cell region to form a substantially rectangular bitcell shape. Other embodiments are described and claimed.