Abstract: Disclosed is a reticle with multiple different sets of redundant mask patterns. Each set allows for patterning of a layer at a specific level of an integrated circuit (IC) chip design on a target region of a wafer using a vote-taking technique to avoid defects. The different sets further allow the same reticle to be used to pattern layers at different levels in the same IC chip design or to pattern layers at the same level or at different levels in different IC chip designs. Each mask pattern is individually framed with alignment marks to facilitate alignment minimize overlay errors. Optionally, redundant mask patterns in the same set are distributed across the reticle (as opposed to being located within the same general area) in order to minimize reticle overheating during patterning using the vote-taking technique. Also disclosed are a photolithography system and a photolithography method that employ such a reticle.

Abstract: A metrology pattern layout for a circuit structure is provided, the metrology pattern layout including a plurality of quadrants, in which quadrants a first wafer measurement pattern, a second wafer measurement pattern, a reticle registration pattern, and a reticle measurement pattern may be arranged to facilitate correlation of reticle metrology data with wafer metrology data. The reticle registration pattern may further include one or more outermost structural elements designed to protect other structural elements within the reticle measurement pattern from being modified in an optical proximity correction process. A method of optical proximity correction process is provided, in which a reticle measurement pattern may be obtained and classified to add or modify a rule set of the optical proximity correction process.

Abstract: A metrology pattern layout for a circuit structure is provided, the metrology pattern layout including a plurality of quadrants, in which quadrants a first wafer measurement pattern, a second wafer measurement pattern, a reticle registration pattern, and a reticle measurement pattern may be arranged to facilitate correlation of reticle metrology data with wafer metrology data. The reticle registration pattern may further include one or more outermost structural elements designed to protect other structural elements within the reticle measurement pattern from being modified in an optical proximity correction process. A method of optical proximity correction process is provided, in which a reticle measurement pattern may be obtained and classified to add or modify a rule set of the optical proximity correction process.

Abstract: A metrology pattern layout for a circuit structure is provided, the metrology pattern layout including a plurality of quadrants, in which quadrants a first wafer measurement pattern, a second wafer measurement pattern, a reticle registration pattern, and a reticle measurement pattern may be arranged to facilitate correlation of reticle metrology data with wafer metrology data. The reticle registration pattern may further include one or more outermost structural elements designed to protect other structural elements within the reticle measurement pattern from being modified in an optical proximity correction process. A method of optical proximity correction process is provided, in which a reticle measurement pattern may be obtained and classified to add or modify a rule set of the optical proximity correction process.

Abstract: An apparatus, system, and method for nanoimprint templates with a backside recess having tapered sidewalls. In some embodiments, the nanoimprint templates comprise a support structure having a top surface, a bottom surface, and a recess in the top surface. The recess may have an inwardly tapered sidewall extending from the top surface to a floor of the recess. The template may further comprise a mold on the bottom surface.

Abstract: A method of generating a design of a reticle for a photolithography process. The reticle may include phase shift features, binary features, and mixed features. The method includes generating a reticle design from a pattern layout and then optimizing the reticle design. In some examples, generating the reticle design includes binning the features of the layout based on feature width. Examples of optimization operations include an over/under operation, an under/over operation, a feature segment expansion operation, a feature edge portion conversation from a binary portion to a phase shift portion, a corner binary segment expansion, a discontinuity removal operation, and a feature dimension change operation that includes a determination of a Mask Error Factor (MEF).

Abstract: A method (100) to manufacture semiconductor reticles associated with a design uses an optical pattern correction (OPC) test pattern (104) in a first reticle frame and having subresolution features that will not resolve or appear on a resulting wafer. A first reticle is made (106) and critical parameters are extracted from the first reticle (108). The critical parameters are used to execute an OPC model (112) to generate a modified design. A production reticle is made from the modified design. The OPC test pattern is placed in a second reticle frame and a second reticle is manufactured. Critical parameters from the second reticle are compared with the critical parameters from the first reticle and must be within a predetermined tolerance or the reticle build process is modified until the tolerance is reached.

Abstract: A process of forming indicia on autoradiograms is disclosed wherein a substrate containing a distribution of radioactive material, such as radioactively tagged proteins, is marked with a hexagonal Wurtzite form of zinc sulfide doped with trace metals phosphor. The thusly marked substrate is exposed to actinic radiation to charge the phosphor. The substrate is then superposed on an X-ray film to form a latent photographic image in the film which is developed by conventional means to form a photographic image of the phosphorescent indicia and the distribution of radioactive material in the substrate.