Abstract: A system for sharing data between two processes implements a memory arranged as a two dimensional ping/pong buffer where a writing operation alternately swaps buffers in one dimension and a reading operation swaps buffers in the other dimension. Accordingly, writing is into one or the other of a reading buffer set not currently being read with each write alternating between the write buffers. Data is retrieved from the buffer that is not currently being written. The buffer switching is coordinated by using commonly accessed variables between the reader and the writer and implements a system that is lock-free.

Abstract: An asynchronous pipeline structure includes a plurality of functional blocks comprising dynamic logic, each block precharged to an idle state responsive to a precharge control signal applied thereto, with each block, upon being precharged, receiving input data thereto for processing, and holding output data generated thereby during an evaluate phase, independent of a reset of the input data; for each block, a completion detector circuit coupled to the output of the functional block, the completion detector circuit generating an acknowledgement signal that indicates validity or absence of data at the output of the block; and for each block, a precharge control circuit generating a precharge signal, wherein for a given block, a first input to the precharge control circuit comprises the acknowledgment signal from a downstream completion detector, and second input to the precharge control circuit comprises the precharge signal from an upstream precharge control circuit.

Abstract: A data flow controller for reconfigurable computers. The novel data flow controller includes a first circuit for selecting one of a plurality of operating conditions and a second circuit for determining if the selected condition is met and outputting a control signal accordingly. In an illustrative embodiment, the operating conditions include: when all enabled data available signals are asserted and all enabled space available signals are asserted; when any enabled data available signal is asserted and all enabled space available signals are asserted; when all enabled data available signals are asserted and any enabled space available signal is asserted; and when any enabled data available signal is asserted and any enabled space available signal is asserted. By allowing a configurable element to operate under different possible conditions, data flow signals can also then be used to control what operation the element performs, in addition to controlling when.

Abstract: A digital signal processing apparatus includes a digital circuit device having one or more elements configured to process digital data; a power supply configured to deliver a controllable operating voltage for the one or more elements; control logic configured to receive feedback signals from each of the one or more elements, the feedback signals indicative of a rate at which data is moving through each individual element; and the control logic configured to output a control signal to the power supply so as to cause the power supply to reduce the operating voltage for the one or more elements responsive to a decreasing workload detected therein, and to cause the power supply to increase the operating voltage for the one or more pipelines responsive to an increasing workload detected therein.

Abstract: An asynchronous pipeline structure includes a plurality of functional blocks comprising dynamic logic, each block precharged to an idle state responsive to a precharge control signal applied thereto, with each block, upon being precharged, receiving input data thereto for processing, and holding output data generated thereby during an evaluate phase, independent of a reset of the input data; for each block, a completion detector circuit coupled to the output of the functional block, the completion detector circuit generating an acknowledgement signal that indicates validity or absence of data at the output of the block; and for each block, a precharge control circuit generating a precharge signal, wherein for a given block, a first input to the precharge control circuit comprises the acknowledgment signal from a downstream completion detector, and second input to the precharge control circuit comprises the precharge signal from an upstream precharge control circuit.

Abstract: A digital signal processing apparatus includes a digital circuit device having one or more elements configured to process digital data; a power supply configured to deliver a controllable operating voltage for the one or more elements; control logic configured to receive feedback signals from each of the one or more elements, the feedback signals indicative of a rate at which data is moving through each individual element; and the control logic configured to output a control signal to the power supply so as to cause the power supply to reduce the operating voltage for the one or more elements responsive to a decreasing workload detected therein, and to cause the power supply to increase the operating voltage for the one or more pipelines responsive to an increasing workload detected therein.

Abstract: Methods for tracking the relative velocity between a vehicle and a target that uses both a measured velocity as well as an estimate of the velocity that is based on tracking the peaks in a laser vibrometer return signal.

Abstract: Methods for tracking the relative velocity between a vehicle and a target that uses both a measured velocity as well as an estimate of the velocity that is based on tracking the peaks in a laser vibrometer return signal.

Abstract: A data flow controller for reconfigurable computers. The novel data flow controller includes a first circuit for selecting one of a plurality of operating conditions and a second circuit for determining if the selected condition is met and outputting a control signal accordingly. In an illustrative embodiment, the operating conditions include: when all enabled data available signals are asserted and all enabled space available signals are asserted; when any enabled data available signal is asserted and all enabled space available signals are asserted; when all enabled data available signals are asserted and any enabled space available signal is asserted; and when any enabled data available signal is asserted and any enabled space available signal is asserted. By allowing a configurable element to operate under different possible conditions, data flow signals can also then be used to control what operation the element performs, in addition to controlling when.

Abstract: In accordance with one aspect of the present invention, a system for tracking a target is provided that includes an image sensor mounted to a gimbal for acquiring an image, wherein the image includes a plurality of pixels representing the target and a background. The system further includes a motor for rotating the gimbal and an autotracker electrically coupled to the image sensor and the motor. The autotracker includes a probability map generator for computing a probability that each of the plurality of pixels having a particular intensity is either a portion of the target or a portion of the background, a pixel processor in communicative relation with the probability map generator for calculating a centroid of the target based upon the probabilities computed by the probability map generator, and a controller in communicative relation with the pixel processor for generating commands to the motor based upon the centroid.

Abstract: In accordance with one aspect of the present invention, a system for tracking a target is provided that includes an image sensor mounted to a gimbal for acquiring an image, wherein the image includes a plurality of pixels representing the target and a background. The system further includes a motor for rotating the gimbal and an autotracker electrically coupled to the image sensor and the motor. The autotracker includes a probability map generator for computing a probability that each of the plurality of pixels having a particular intensity is either a portion of the target or a portion of the background, a pixel processor in communicative relation with the probability map generator for calculating a centroid of the target based upon the probabilities computed by the probability map generator, and a controller in communicative relation with the pixel processor for generating commands to the motor based upon the centroid.

Abstract: Systems and methods for improving the intensity equalization of image data obtained with systems that perceive images with energy sources other than visible light includes a sensor for such data; a converter for transforming the image data from analog form to digital form; a converter for transforming the digital data into black-and-white images containing a predetermined, desired number of gray shades; an intensity equalizer that compensates for the logarithmic effect of visual images on a human eye; an intensity equalizer that compensates for the non-linear effect of the display device for the data; and a converter for transforming the digital intensity-equalized black-and-white image data into analog form for display on a device such as a conventional CRT.

Abstract: A combined scene-based and DC-restored image restoration system enhances the utility of video images generated from the input of a forward-looking infrared system. This system and related methods remove a desired portion of the DC content from each of a plurality of input signals that are generated from a plurality of adjacent portions of a source image to obtain a plurality of resultant signals from which a plurality of video images is produced.

Abstract: A heads-up display (50) for an aircraft includes a digital image generator (52), a cathode ray tube (CRT) (54) and an optical system (56) which projects an image (58) formed on the CRT screen (54a) indicating the status of the aircraft operation onto a holographic mirror combiner (60) at a slant angle. The combiner (60) is transparent to the pilot's direct view through the aircraft windshield, but produces a reflected image of the CRT screen (54a) which is superimposed on the direct view. Pincushion distortion in the CRT (54) and geometric distortion caused by the slant projection angle are corrected by a digital look-up table memory (82, 84) which alters the initially orthogonal CRT horizontal and vertical deflection signals (Vh,Vv) in a manner which is the inverse of the distortion such that the image (58) on the combiner (60) as viewed by the pilot appears undistorted.