Patents by Inventor Lloyd L. Lautzenhiser

Lloyd L. Lautzenhiser has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220049503
    Abstract: A method for producing a surface covering system comprising magnetically receptive layers affixed to surface covering units and magnetized underlayments for use in securing surface covering units to supporting surfaces. The system includes isotropic magnetized floor covering units and anisotropic magnetized underlays for securing surface covering units. The system includes a set of formulations including ferrites and rare earth materials, oils and plasticizer and binding agents to optimize performance to meet design and application criteria.
    Type: Application
    Filed: January 20, 2020
    Publication date: February 17, 2022
    Inventors: Shane S. Leblanc, Lloyd L. Lautzenhiser, Melinda Leblanc
  • Publication number: 20200171810
    Abstract: The present invention pertains to the art of floor coverings, and, more particularly to an apparatus for use in securing floor covering units to an underlay and a method of manufacturing said floor covering units and said underlay. More particularly, the present invention relates to an apparatus, method, and method of manufacturing magnetized floor covering units and magnetized underlays for securing magnetized floor covering units.
    Type: Application
    Filed: October 29, 2019
    Publication date: June 4, 2020
    Applicant: Golconda Holdings LLC
    Inventors: Lloyd L. Lautzenhiser, Shane S. LeBlanc, Melinda LeBlanc
  • Patent number: 10616013
    Abstract: An electronic assembly including a plurality of electrically conductive elements separated by insulative material and a digital FM demodulator circuit coupled to some of the electrically conductive elements. The FM demodulator circuit having an FM detector circuit and a DC drift reducing circuit. The FM detector circuit has a detector input and a detector output that is the output of a comparator that is AC coupled to the rest of the FM detector circuit, the detector input receiving an input signal. The DC drift reducing circuit is electrically coupled to the detector output of the comparator, the DC drift reducing circuit detecting a DC drift of the detector output, the DC drift reducing circuit being additionally coupled to an input of the comparator, the DC drift reducing circuit substantially eliminating DC drift at the output of the FM demodulator circuit.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: April 7, 2020
    Assignee: Emhiser Research Limited
    Inventor: Lloyd L. Lautzenhiser
  • Publication number: 20190390466
    Abstract: The present invention pertains to the art of surface coverings, and, more particularly to a system and method for producing isotropic and anisotropic magnetically receptive layers and magnetized underlayments for use in securing surface covering units supporting surfaces. The present invention relates to an apparatus, method, and method of manufacturing isotropic and anisotropic magnetized floor covering units and magnetized underlays for securing surface covering units.
    Type: Application
    Filed: March 29, 2019
    Publication date: December 26, 2019
    Inventors: Lloyd L. Lautzenhiser, Shane S. LeBlanc, Melinda LeBlanc
  • Patent number: 10457031
    Abstract: The present invention pertains to the art of floor coverings, and, more particularly to an apparatus for use in securing floor covering units to an underlay and a method of manufacturing said floor covering units and said underlay. More particularly, the present invention relates to an apparatus, method, and method of manufacturing magnetized floor covering units and magnetized underlays for securing magnetized floor covering units.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: October 29, 2019
    Assignee: Golconda Holdings, LLC
    Inventors: Lloyd L. Lautzenhiser, Shane S. LeBlanc, Melinda LeBlanc
  • Patent number: 10277231
    Abstract: An electronic assembly having a phase locked discriminator circuit that includes a phase locked loop (PLL), a voltage controlled oscillator (VCO), a signal output integrator, and a direct current (DC) drift reducing circuit. The PLL has an input to receive an oscillating signal. The signal output integrator, the PLL and the VCO are all electrically coupled together. The DC drift reducing circuit is electrically coupled to the PLL, the signal output integrator and the VCO. The DC drift reducing circuit detects a DC drift of an output of the signal output integrator by comparing a frequency of the oscillating signal to the DC drift.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: April 30, 2019
    Assignee: Emhiser Research Limited
    Inventor: Lloyd L. Lautzenhiser
  • Publication number: 20190063075
    Abstract: The present invention provides a system, method, and apparatus for installing modular wood, engineered hardwood, and hardwood surface covering units on walls, floors, and other surfaces. The modular surface covering units have multiple layers. The layers are an outer layer, a wood, engineered hardwood, or hardwood layer, and a magnetic layer. Other layers or combinations of layers may also be used.
    Type: Application
    Filed: June 20, 2018
    Publication date: February 28, 2019
    Inventors: Lloyd L. Lautzenhiser, Shane S. LeBlanc, Melinda LeBlanc, Li Huang
  • Patent number: 10189236
    Abstract: The present invention pertains to the art of floor coverings, and, more particularly to an apparatus for use in securing floor covering units to an underlay and a method of manufacturing said floor covering units and said underlay. More particularly, the present invention relates to an apparatus, method, and method of manufacturing magnetized floor covering units and magnetized underlays for securing magnetized floor covering units.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: January 29, 2019
    Assignee: Golconda Holdings, LLC
    Inventors: Lloyd L. Lautzenhiser, Shane S. LeBlanc, Melinda LeBlanc
  • Patent number: 9850923
    Abstract: A hydraulic jack including a load cylinder, a pump, a release valve and a flow regulator. The pump is configured to provide pressurized fluid to the load cylinder. The release valve is in fluid communication with the pressurized fluid. The flow regulator is configured to alter a flow path of the fluid therethrough as an inverse function of a pressure drop of the fluid across the flow regulator. The fluid regulator being in fluid communication with the release valve.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: December 26, 2017
    Assignee: Brookefield Hunter, Inc.
    Inventors: Lloyd L. Lautzenhiser, Wade Wolf
  • Patent number: 9824801
    Abstract: An electrical assembly including a conductor arrangement and a dual resolution potentiometer electrically connected to the conductor arrangement. The dual resolution potentiometer includes a first resistive element having a first adjustment mechanism and a second resistive element having a second adjustment mechanism. The first adjustment mechanism being coupled in a hysteresis arrangement to the second adjustment mechanism.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: November 21, 2017
    Assignee: Emhiser Research Limited
    Inventor: Lloyd L. Lautzenhiser
  • Patent number: 9787271
    Abstract: A feedback gate bias circuit for use in radio frequency amplifiers to more effectively control operation of LDFET, GaNFET, GaAsFET, and JFET type transistors used in such circuits. A transistor gate bias circuit that senses drain current and automatically adjusts or biases the gate voltage to maintain drain current independently of temperature, time, input drive, frequency, as well as from device to device variations. Additional circuits to provide temperature compensation, RF power monitoring and drain current control, RF output power leveler, high power gain block, and optional digital control of various functions. A gate bias circuit including a bias sequencer and negative voltage deriver for operation of N-channel depletion mode devices.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: October 10, 2017
    Assignee: EMHISER RESEARCH LIMITED
    Inventor: Lloyd L Lautzenhiser
  • Patent number: 9741478
    Abstract: An electrical assembly including a conductor arrangement and a multi-resolution potentiometer electrically connected to the conductor arrangement. The multi-resolution potentiometer includes a first resistive element having a first adjustment mechanism and a first wiper, and a second resistive element having a second adjustment mechanism and a second wiper. The first adjustment mechanism is coupled in a hysteresis arrangement to the second adjustment mechanism. A resistor network provides an electrical output for the potentiometer and electrically couples the first wiper with the second wiper.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: August 22, 2017
    Assignee: Emhiser Research Limited
    Inventor: Lloyd L. Lautzenhiser
  • Patent number: 9648972
    Abstract: A seaming apparatus is formed from an elongated plate that is inextendible in both longitudinal and lateral directions. An upper surface of the plate is divided into multiple, transversely spaced and longitudinally extending zones. In the preferred embodiment, three such zones, including two edge zones spaced by a central zone, are provided. Numerous elongated upstanding sharp projections are provided in each of the edge zones and an adhesive layer is provided in the central zone. A peelable protective cover is arranged atop the adhesive layer. A thin adhesive layer with a peelable protective cover may be placed on a lower surface to secure the seaming apparatus to a supporting surface.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: May 16, 2017
    Assignee: Armorlock Industries, LLC
    Inventors: Shane S LeBlanc, Lloyd L Lautzenhiser
  • Publication number: 20170133132
    Abstract: An electrical assembly including a conductor arrangement and a multi-resolution potentiometer electrically connected to the conductor arrangement. The multi-resolution potentiometer includes a first resistive element having a first adjustment mechanism and a first wiper, and a second resistive element having a second adjustment mechanism and a second wiper. The first adjustment mechanism is coupled in a hysteresis arrangement to the second adjustment mechanism. A resistor network provides an electrical output for the potentiometer and electrically couples the first wiper with the second wiper.
    Type: Application
    Filed: January 13, 2017
    Publication date: May 11, 2017
    Applicant: Emhiser Research Limited
    Inventor: Lloyd L. Lautzenhiser
  • Patent number: 9617129
    Abstract: A hydraulic jack includes a frame and a pump connected to the frame. The pump is connected to the frame. The pump includes a rod, a housing, and a piston, with hydraulic fluid being in the housing. The rod has a cross-sectional area and has a longitudinal axis. The housing has an end through which the rod slides. The housing has an interior open cross-sectional area in a direction normal to the longitudinal axis, and the housing has an interior wall. The piston is coupled to the rod. The piston establishes a rod side chamber and a piston side chamber within the housing. The piston has a cross-sectional area, which is smaller than the cross-sectional area of the housing thereby allowing a portion of the hydraulic fluid to flow between said piston and said interior wall to and from the rod side chamber and the piston side chamber when the piston is moved in the housing.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: April 11, 2017
    Assignee: Brookefield Hunter, Inc.
    Inventors: Lloyd L. Lautzenhiser, Wade Wolf
  • Publication number: 20170093353
    Abstract: A feedback gate bias circuit for use in radio frequency amplifiers to more effectively control operation of LDFET, GaNFET, GaAsFET, and JFET type transistors used in such circuits. A transistor gate bias circuit that senses drain current and automatically adjusts or biases the gate voltage to maintain drain current independently of temperature, time, input drive, frequency, as well as from device to device variations. Additional circuits to provide temperature compensation, RF power monitoring and drain current control, RF output power leveler, high power gain block, and optional digital control of various functions. A gate bias circuit including a bias sequencer and negative voltage deriver for operation of N-channel depletion mode devices.
    Type: Application
    Filed: February 19, 2015
    Publication date: March 30, 2017
    Inventor: Lloyd L. Lautzenhiser
  • Publication number: 20170081159
    Abstract: A method of extending a jack including the steps of: first stage pumping by passing pressurized fluid at a first pressure and a first volume to a jack cylinder primarily by movement of a piston; and second stage pumping by passing pressurized fluid at a second pressure and a second volume to the jack cylinder primarily by movement of a rod connected to the piston.
    Type: Application
    Filed: November 29, 2016
    Publication date: March 23, 2017
    Applicant: Brookfield Hunter, Inc.
    Inventors: Lloyd L. Lautzenhiser, Wade Wolf
  • Publication number: 20170084369
    Abstract: An electrical assembly including a conductor arrangement and a dual resolution potentiometer electrically connected to the conductor arrangement. The dual resolution potentiometer includes a first resistive element having a first adjustment mechanism and a second resistive element having a second adjustment mechanism. The first adjustment mechanism being coupled in a hysteresis arrangement to the second adjustment mechanism.
    Type: Application
    Filed: November 30, 2016
    Publication date: March 23, 2017
    Applicant: Emhiser Research Limited
    Inventor: Lloyd L. Lautzenhiser
  • Patent number: 9558870
    Abstract: An electrical assembly including a conductor arrangement and a dual resolution potentiometer electrically connected to the conductor arrangement. The dual resolution potentiometer includes a first resistive element having a first adjustment mechanism and a second resistive element having a second adjustment mechanism. The first adjustment mechanism being coupled in a hysteresis arrangement to the second adjustment mechanism.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: January 31, 2017
    Assignee: Emhiser Research Limited
    Inventor: Lloyd L. Lautzenhiser
  • Publication number: 20160375673
    Abstract: The present invention pertains to the art of floor coverings, and, more particularly to an apparatus for use in securing floor covering units to an underlay and a method of manufacturing said floor covering units and said underlay. More particularly, the present invention relates to an apparatus, method, and method of manufacturing magnetized floor covering units and magnetized underlays for securing magnetized floor covering units.
    Type: Application
    Filed: March 28, 2016
    Publication date: December 29, 2016
    Inventors: Lloyd L. Lautzenhiser, Shane S. LeBlanc, Melinda LeBlanc