Abstract: The present invention relates to a conventionally shaped golf bag for carrying golf clubs and accessories. The golf bag is open at the top end for insertion of golf clubs, includes a shoulder strap, a stand, and an electronic command station. The electronic command station includes a number of modules, enabling the communication and its control by a command station application operating in association with a mobile electronic device. The communication module may be a transceiver wirelessly connecting between the mobile electronic device and a cellular telephone network. The electronic command station may include a display, a rechargeable battery, and one or more electronics connection ports for communicating with and charging one or more mobile electronic devices. The electronic command station is mounted in association with the external face of a golf bag such that the display is externally accessible.

Abstract: A dwelling power management system includes a smart power integrated node located at a dwelling and configured to transit information to and receive information from a remote server arrangement. The smart power integrated node selectively controls power applied to dwelling electrical power hardware components according to a recommended operating procedure (ROP). The system also includes a utility switch connected to the smart power integrated node, the utility switch configured to control distribution of electrical power received from a dwelling external power source. The smart power integrated node transmits dwelling power usage information and dwelling user preferences to the remote server arrangement that evaluates relevant information including dwelling power usage information and dwelling user preferences and dwelling external factors to develop an optimized ROP. The smart power integrated node operates according to the optimized ROP.

Abstract: A dwelling power management system includes a smart power integrated node located at a dwelling and configured to transit information to and receive information from a remote server arrangement. The smart power integrated node selectively controls power applied to dwelling electrical power hardware components according to a recommended operating procedure (ROP). The system also includes a utility switch connected to the smart power integrated node, the utility switch configured to control distribution of electrical power received from a dwelling external power source. The smart power integrated node transmits dwelling power usage information and dwelling user preferences to the remote server arrangement that evaluates relevant information including dwelling power usage information and dwelling user preferences and dwelling external factors to develop an optimized ROP. The smart power integrated node operates according to the optimized ROP.

Abstract: A multi-standard indoor mobile radio access network is provided. Preferred embodiments of the present invention operate in accordance with a plurality of radio heads and at least one gateway/router. In one embodiment of the present invention, each radio head is configured to use a signal received from a wireless device to detect a corresponding service provider. Each radio is also configured to detect a power level of the signal, as received. Data is then communicated to the gateway/router, including at least radio head identification numbers, z-axis information (e.g., as stored in each radio head, etc.), the channels used, service provider identifiers, and power levels (e.g., as received by each radio head). The gateway/router is then configured to use at least the power levels and z-axis information provided by the plurality of radio heads to determine a location (e.g., z-axis location, or floor) of the wireless device.

Abstract: According to one embodiment of the invention, a summing circuit comprises a first transmitter, a second transmitter, a first current offset circuit and a first transconductance amplifier. The first current offset circuit is coupled to the emitters of the first and second transistors. The first transconductance amplifier is coupled to the first current offset circuit.

Abstract: According to one embodiment of the invention, a programmable finite impulse response (FIR) filter is implemented with differential isolation circuits to isolate parasitic capacitance from attenuating an output signal at both first and second differential output terminals of the FIR filter. The FIR includes a track and hold circuit and a summing circuit that provides operational advantages to the FIR filter.

Abstract: According to one embodiment of the invention, a programmable finite impulse response (FIR) filter is implemented with differential isolation circuits to isolate parasitic capacitance from attenuating an output signal at both a first and second differential output terminals of the FIR filter. The FIR includes a summing circuit that provides operational advantages to the FIR filter.

Abstract: According to one embodiment of the invention, a programmable finite impulse response (FIR) filter is implemented with differential isolation circuits to isolate parasitic capacitance from attenuating an output signal at both a first and second differential output terminals of the FIR filter. The FIR includes a track and hold circuit and a summing circuit that provides operational advantages to the FIR filter.

Abstract: Disclosed is a LADAR system and a method for operating same. The LADAR system includes circuitry for generating the electrical signal with an optical signal detector using N discrete samples; a bank of M parallel sample/hold circuit unit cells individual ones of which operate with an associated sample/hold clock, where each sample/hold clock is shifted in time by a fixed or programmable amount ?t relative to a sample/hold clock of an adjacent sample/hold circuit unit cell; and further includes circuitry for sequentially coupling a sampled value of the electrical signal from a first output of individual ones of at least some of the M parallel sample/hold circuit unit cells to an analog to digital converter circuit. Each of the M parallel sample/hold circuit unit cells has a second output for outputting a digital signal for indicating the state (low or high) during a time that the associated sample/hold clock allowing for time of arrival determination.

Abstract: A multi-mode analog to, digital converter (ADC). The novel ADC includes an input terminal for receiving an analog input signal; a plurality of processing stages, each processing stage adapted to generate an output signal from an input to that processing stage; and a mechanism for determining a mode of operation and in accordance therewith connect the processing stages and the input terminal in a predetermined configuration. In an illustrative embodiment, the ADC can be configured as a subranging ADC, and the mechanism for determining, the mode of operation includes a signal processor for automatically selecting the mode of operation based on the frequency components of the input signal.

Abstract: A low distortion amplifier. The novel amplifier includes a first transistor Q1 having first and second output terminals and an input terminal adapted to receive an input signal, and a second transistor Q2 having first and second output terminals and an input terminal adapted to receive a signal from the first output terminal of Q1, wherein the second output terminal of Q1 is connected to the second output terminal of Q2 in order to eliminate a nonlinear current component in Q2. In an illustrative embodiment, the amplifier also includes a cascode Darlington pair Q3, Q4 for holding the second output terminals of Q1 and Q2 at a desired voltage to further reduce distortion and to maintain a wide bandwidth.

Abstract: An output driver. The novel output driver includes a first circuit for receiving an input signal and in accordance therewith generating an output signal at an output node, a second circuit for applying a variable current to the output node, and a third circuit for controlling the magnitude of the variable current in accordance with the input signal. In an illustrative embodiment, the third circuit is adapted to generate a controlling current in accordance with the input signal, and the second circuit includes a current mirror adapted to receive the controlling current and output a scaled version of the controlling current to the output node.

Abstract: A trimmable comparator. The novel comparator includes a first circuit for comparing first and second input signals and in accordance therewith generating first and second output signals, and a second circuit for adding an adjustable current to the first output signal such that the comparator is in a transition state when the first and/or second input signals are at desired levels. The comparator may also include a third circuit for adding an adjustable current to the second output signal. In the illustrative embodiments, the second and third circuits are implemented using adjustable current sources with trimmable resistors, or using digital to analog converters. The novel comparators may be used in an analog to digital converter to allow the converter thresholds to be adjusted to desired levels.

Abstract: A high speed switch. The novel switch includes an input circuit having a transistor Q1 for receiving an input signal, a first mechanism for providing a path from an output of Q1 to an output terminal, and a second mechanism for receiving a control signal and in accordance therewith reducing the conductivity of the path during a mute mode. The first mechanism includes a first circuit for providing a first path from an output of Q1 to a first node, and a second circuit for providing a second path connecting the first node to the output terminal. The second mechanism is adapted to apply a signal to the first node during the mute mode such that the first and second circuits are off or partially conducting. The switch also includes a circuit for clamping the first node to a first predetermined voltage during the mute mode.

Abstract: An amplifier. The novel amplifier includes a first circuit for receiving and amplifying an input signal and outputting an output signal, and a second circuit for supplying power to the first circuit, wherein the power supplied varies in accordance with variations in the output signal. The second circuit includes a bootstrapping circuit adapted to regulate the voltages across any transistors in the signal path such that the voltages remain constant. In an illustrative embodiment, the second circuit bootstraps the voltages across a PMOS current source that acts as the load to an input stage, as well as a Darlington pair in an output stage of the amplifier.

Abstract: A clamped comparator. The novel comparator includes a first circuit for comparing first and second input signals and generating a digital output, and a second circuit for receiving a control signal and in accordance therewith decoupling the input signals from the output. The second circuit includes one or more switching circuits adapted to clamp the signal path between the input signals and the output when the circuit is operating in a ‘mute’ mode. In an illustrative embodiment, the comparator also includes a pre-amplifier with an amplifier stage, and the switching circuit is adapted to turn off the amplifier stage and/or steer the outputs of the amplifier stage out of the signal path, when the circuit is in the ‘mute’ mode.

Abstract: A DAC (10) including an operational amplifier (12) having an input terminal; a plurality of current paths coupled to the input terminal; a plurality of current sources (I1/2-I4/2); and an arrangement (11) for switchably coupling current from at least two of the cells to a respective one of the paths in response to an input signal. In a specific embodiment, the inventive DAC (10) further includes a first resistive element (2R1-2R4) disposed in each of the current paths, a second resistive element (R1-R4) disposed between the current paths, and a feedback resistor (RF) disposed between an output terminal of the amplifier and the input terminal thereof. In the illustrative embodiment, the coupling arrangement includes a plurality of switches (SW1-SW4); each of the switches is adapted to switch half of the current from a first source and half of the current from a second source into a respective one of the paths.

Abstract: A subtraction circuit. The novel subtraction circuit includes a first circuit for providing an impedance between an input node and an output node, a second circuit for generating a first current and applying the first current to the output node to produce a desired voltage drop between the input and output nodes, and a third circuit for independently generating a second current relative to the first current and applying the second current to the input node to regulate a current input to the first circuit at the input node. The second and third circuits are implemented using two digital to analog converters (DACs), a precision DAC for generating the first current and a non-trimmed “dummy” DAC for generating the second current. In an illustrative embodiment, the subtraction circuit is used in the reconstruction stage of a subranging analog to digital converter.

Abstract: A sample and hold circuit including a first arrangement for receiving an input signal; a second arrangement for sampling and holding the signal in response to a control signal; and a third arrangement for minimizing the change in an input transistor's base current when the circuit switches from track to hold or hold to track and for keeping the collector emitter voltage constant at the input transistor. An arrangement is disclosed to increase the dynamic current accuracy of a current mirror for a diode connected transistor, by holding the voltage across one transistor in the current mirror constant. Another arrangement is disclosed for holding collector to emitter voltage constant for intermediate transistors resulting in improved gain accuracy and linearity. In one embodiment, a dummy leg is added to isolate the output voltage from switching transients that occur when an intermediate transistor is turned on at the transition from track to hold.

Abstract: A subranging analog to digital converter (ADC). The ADC (200) includes a novel resistive ladder (56) for a differential quantizer (50) and a novel summing node circuit (150). The novel resistive ladder (56) includes an input terminal (52), a plurality of serially connected resistors R coupled to the input terminal (52), and a pair of complementary current sources (66 and 68) for maintaining a constant current flow through the ladder (56). The novel summing node circuit (150) includes an input terminal (152) for receiving an input signal, a pair of complementary DACs (156 and 158) for generating a reconstruction signal, and a summing amplifier (164) for subtracting the reconstruction signal from the input signal to produce a residue signal. The invention also includes a method for trimming the subranging ADC.