Abstract: A circuit implements a method to adjust input/output (I/O) characteristics of an I/O pad circuit (10) depending upon which value of an I/O supply voltage is used within a range of supply voltages. An I/O supply voltage being supplied to the pad circuit is detected by detecting (18, 20) its value relative to a known reference (16). Portions of the I/O pad circuit are selectively enabled in response to the detected I/O supply voltage. By selecting the ratio of P-channel and N-channel transistors, physical characteristics of the circuit are controlled. Examples of the controlled physical characteristics include slew rate, signal rise and fall times, and duty cycle control which is controlled by forcing all rising and falling edges to have a midpoint at the same point in time. Therefore a same I/O pad circuit may be optimally used in numerous applications regardless of the supply voltage value.

Abstract: An output buffer (100) contains a low voltage driver (110), a medium voltage driver (108), and a high voltage driver (106). When an output pad (112) is configured to operate between ground and the medium voltage, the low voltage driver (110) is first used during low-to-high transitions to drive the output pad (112) from ground to an intermediate voltage in a fast manner. After the intermediate voltage is obtained on the output pad (112), a detection circuit (111) will switch output pad control from the low voltage driver (110) to the medium voltage driver (108). The medium voltage driver (108) will drive the output pad (112) from the intermediate voltage to the final logic one output voltage. This two-stage low-to-high driving methodology ensures that there will be less delay time from input (DO) to the output pad (112).

Abstract: A module for controlling an output signal in a system including first and second power supply signals. The module includes a comparator coupled to receive the first power supply signal and a second signal and coupled to provide a control signal. Also included is a pad module coupled to receive the first power supply signal and the control signal and coupled to provide an output signal. The output signal of the pad module is disabled when the control signal has a first value. Various aspects of the present invention may also be realized through a power-on disable module for an apparatus having multiple power supply signals. The power-on disable module includes a controller coupled to receive a plurality of power supply signals and coupled to provide a power-on disable signal depending on a comparison of the power supply signals.

Abstract: A protection circuit (13) for an integrated circuit (10) is capable of handling higher externally-provided voltages supplied to internal circuitry within the integrated circuit (10). The protection circuit (13) comprises a zener diode (20), wherein a N+ type diffusion region (38) is separated from a P field implant (40) lying between the N+ type diffusion region (38) and a P+ type diffusion region (39).

Abstract: An integrated circuit (20) configures the active level of an input, output, or input/output pin by sensing a logic state on the pin's bonding pad (21) at the inactivation of a reset signal, such as a power-on reset signal. The integrated circuit (20) selects a true or complement signal to provide to or from an internal circuit (25). The voltage level on the pin is latched on the active-to-inactive transition of the power-on reset signal. Thus, the use of proper board-level termination resistors (70, 71) programs the pins to the desired active logic level without the need for additional logic circuitry or a dedicated device pin.

Abstract: In a data processing system having an ALU and a memory, a decode/driver circuit has a dynamic node in which the voltage variation of the node is controlled. When the circuit is enabled, the dynamic node is precharged to a predetermined voltage potential which drives an output drive transistor. The output drive transistor couples a decoded select signal to an output terminal and inadvertently causes the dynamic node's voltage potential to change, thereby negatively affecting the voltage at the output terminal. To compensate, a transistor is provided which connects a predetermined voltage terminal to the dynamic node in response to the voltage at the output terminal.

Abstract: A phase locked loop has a digital phase comparator, a filter with multiple bandwidths, a voltage controlled oscillator and a frequency divider connected to the phase comparator to complete the loop. Control circuitry is coupled to both the phase comparator and filter for controlling switching between a wide bandwidth and a narrow bandwidth. The switching in bandwidth is in response to either detecting when the output signal is within a predetermined range of the reference frequency for a predetermined time period or detecting when the output signal exceeds and falls below the reference frequency a predetermined number of times. The control circuit is implemented with circuitry which accurately detects either condition and is capable of blocking any premature change of bandwidth.