Abstract: A differential transceiver transmission line integrity detector detects both open and short circuits in the transmission lines. The two transmission lines are terminated at both ends by selected impedances. A driver coupled to each of the transmission lines drives the lines with data signals. Signal levels on the lines are detected and compared with expected levels to generate line integrity indications. Both open and short conditions are detected and indicated by the line integrity indications.

Abstract: An automatic address assignment system has a plurality of I/O devices coupled to a bus. Each device contains a unique machine-readable identifier which is used to select the device for address assignment. The identifier is a binary bit string. Each bit position in the bit string is selected by the host in a serial manner with the host specifying which binary value is being solicited. All devices whose identifier digit matches the solicited value respond positively and remain in contention for address assignment. The other devices will not respond and drop out of contention for address assignment until the sequence is restarted from the first bit. After the bit sequence is completed, the address for that device is bused to the device, and the sequence is restarted from the first bit until all devices have been assigned an address.

Abstract: Error information is passed across a limited interface from a disk drive to its using system by making use of the read data line during a fault mode operation. Fault mode operation is detected by a pulse width detector in an adapter between the using system and the disk drive. The pulse width detector detects the presence of a fault signal on the read data line and inhibits the passage of the spindle motor on (MTR ON) signal from the using system to the disk drive. The step signal normally used to index the recording head is passed to the disk drive during fault mode operation. A microcomputer at the disk drive detects the absence of the MTR ON signal and the presence of the step signal and outputs a fault data bit. Thereafter, the fault data word is gated onto the read data line at the rate of one bit per step of the step signal so long as the MTR ON signal is absent.