Abstract: An ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.

Abstract: An ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.

Abstract: An ESD protection circuit is formed at the input/output interface contact of an integrated circuit to protect the integrated circuit from damage caused by an ESD event. The ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.

Abstract: An ESD protection circuit is formed at the input/output interface contact of an integrated circuit to protect the integrated circuit from damage caused by an ESD event. The ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.

Abstract: A ring oscillator circuit device is achieved. The device comprises an odd number of inverting stages. Each inverting stage has an input terminal and an output terminal. The inverter stages are coupled in a ring such that the output terminals of preceding inverting stages are coupled to the input terminals of subsequent inverting stages. A variable capacitor is included. The variable capacitor comprises a conductive layer overlying a bulk semiconductor region with a dielectric layer therebetween. The conductive layer is coupled to the output terminal of one of the inverting stages. The value of the variable capacitor depends on a bulk voltage that is coupled to the bulk semiconductor region. The ring oscillator is used for analyzing load dependence of hot carrier injection. The ring oscillator is used as a voltage-controlled oscillator in a phase-locked loop circuit.

Abstract: A ring oscillator circuit device is achieved. The device comprises an odd number of inverting stages. Each inverting stage has an input terminal and an output terminal. The inverter stages are coupled in a ring such that the output terminals of preceding inverting stages are coupled to the input terminals of subsequent inverting stages. A variable capacitor is included. The variable capacitor comprises a conductive layer overlying a bulk semiconductor region with a dielectric layer therebetween. The conductive layer is coupled to the output terminal of one of the inverting stages. The value of the variable capacitor depends on a bulk voltage that is coupled to the bulk semiconductor region. The ring oscillator is used for analyzing load dependence of hot carrier injection. The ring oscillator is used as a voltage-controlled oscillator in a phase-locked loop circuit.

Abstract: A first on-chip test structure monitors hot carrier degradation. A degrading ring oscillator is subjected to hot carrier effects while a non-degrading ring oscillator is not. As the device ages, hot carrier effects degrade the degrading ring counter. The second test structure monitors TDDB degradation. A plurality of N parallel connected capacitors have a stress voltage applied to them such that the time to failure of the first capacitor is the same that experienced by percentage of gates under normal usage. A drop in the resistance indicates breakdown of a capacitor. The third test structure monitors electromigration degradation. M minimum width metal lines are connected in parallel. A current is applied such that the time to failure of all metal lines is the same as that experienced by a percentage of minimum width metal lines under normal usage. An increase in resistance indicates breakdown of a metal line.

Abstract: Described is a system with three on chip monitoring test structures. If any of the three test structures indicates an end of life failure, a bit will be set indicating that the IC is near failure and should be replaced. This is done prior to actual device failure and will eliminate down time of the system where this IC is used. The first test structure monitors hot carrier degradation and is comprised of two ring oscillators. One is subjected to hot carrier effects (degrading ring oscillator) and the other is not subjected to hot carrier effects (non-degrading ring oscillator). Initially, both ring oscillators will each have fixed frequencies, but as the device ages, hot carrier effects degrade the degrading ring counter. Using the non-degrading ring oscillator, the degradation can be quantified and flag a failure. The second test structure monitors TDDB degradation.

Abstract: Described are structures for a device with a controllable dummy layer which can provide a low controllable trigger voltage and can be used as a first triggered device in ESD protection networks. A controllable dummy layer diode is provided which is structured as a butting diode with a dummy polysilicon layer above the butting region. The dummy polysilicon layer functions as an STI block to remove the STI between the n+ and p+ regions of the diode. In one embodiment the diode has the function of a controllable gate with a punchthrough-like-trigger, in which a capacitor-couple circuit couples a portion of the ESD voltage into the gate of the diode to provide a gate voltage.

Abstract: Described are structures for a device with a controllable dummy layer which can provide a low controllable trigger voltage and can be used as a first triggered device in ESD protection networks. A controllable dummy layer diode is provided which is structured as a butting diode with a dummy polysilicon layer above the butting region. The dummy polysilicon layer functions as an STI block to remove the STI between the n+ and p+ regions of the diode. In one embodiment the diode has the function of a controllable gate with a punchthrough-like-trigger, in which a capacitor-couple circuit couples a portion of the ESD voltage into the gate of the diode to provide a gate voltage.

Abstract: Described are structures for a device with a controllable dummy layer which can provide a low controllable trigger voltage and can be used as a first triggered device in ESD protection networks. A controllable dummy layer diode is provided which is structured as a butting diode with a dummy polysilicon layer above the butting region. The dummy polysilicon layer functions as an STI block to remove the STI between the n+ and p+ regions of the diode. In one embodiment the diode has the function of a controllable gate with a punchthrough-like-trigger, in which a capacitor-couple circuit couples a portion of the ESD voltage into the gate of the diode to provide a gate voltage. By changing the channel length under the gate of the diode as well as the gate voltage, the reverse-biased voltage of the diode is readily adjusted to a predetermined level. In a second embodiment the p+ region of the diode overlaps the n+ region turning the diode into a zener diode.