Abstract: A semiconductor package structure includes a lead frame, a chip and a molding compound. The lead frame includes a tray pad and a plurality of leads. Two of the leads are different in height positions. The chip is disposed on the tray. The molding compound encapsulates the chip and a portion of each lead.

Abstract: A semiconductor package structure includes a lead frame, a chip and a molding compound. The lead frame includes a tray pad and a plurality of leads. Two of the leads are different in height positions. The chip is disposed on the tray. The molding compound encapsulates the chip and a portion of each lead.

Abstract: A digital-to-analog converting system with sampling rate conversions includes an interpolator, S orders of operating and filtering units, an up-converting and down-converting circuit, and a signal processing circuit. The interpolator performs an N-times interpolation on a first digital input signal to generate a second digital input signal. Each order of the operating and filtering unit includes a K-times zero-padding circuit and a filtering circuit. The filtering circuit performs a filtering operation to generate a filtered digital input signal. The up-converting and down-converting circuit performs a B-times up-conversion and an A-times down-conversion on the filtered digital input signal to generate a fourth digital input signal. The signal processing circuit generates an analog output signal according to the fourth digital input signal.

Abstract: A digital-to-analog converting system with sampling rate conversions includes an interpolator, S orders of operating and filtering units, an up-converting and down-converting circuit, and a signal processing circuit. The interpolator performs an N-times interpolation on a first digital input signal to generate a second digital input signal. Each order of the operating and filtering unit includes a K-times zero-padding circuit and a filtering circuit. The filtering circuit performs a filtering operation to generate a filtered digital input signal. The up-converting and down-converting circuit performs a B-times up-conversion and an A-times down-conversion on the filtered digital input signal to generate a fourth digital input signal. The signal processing circuit generates an analog output signal according to the fourth digital input signal.

Abstract: An apparatus and method for minimizing the quantization noise as muting are provided, and particularly applied to a Delta-Sigma modulator that is used to process digital-to-analog conversion. By means of a zero-sampling detection circuit and a dynamic gain mechanism, a dynamic gain is introduced to minimize the quantization noise occurred as muting. The method preferably includes a first step for receiving the signals by the Delta-Sigma modulator inputted from an audio decoder, and a next step for detecting signal zero by a zero-sampling detection unit and counting the number of the signals with signal zero. The mute state is entered when the number of signal zeros reaches a pre-set number. At the moment, the signaling route is switched to another route with dynamic gain mechanism. Further, the dynamic gain mechanism is activated for producing a dynamic gain, which will be fed back to the input end of the modulator.