Abstract: An analog to digital converter comprises an input for receiving an analog input signal; a plurality of outputs for outputting parallel bits of a digital signal that represents said analog input signal; and a neural network layer providing connections between each of said outputs respectively, each connection having an adjustable weighting. The synapses of the neural networks may be memristors and training may use online gradient descent.

Abstract: A digital to analog converter is constructed using a neural network layer. The converter has inputs for receiving parallel bits of a digital input signal and an output for outputting an analog signal which is based on the digital input. Connecting the input and the output is a neural network layer which is configured to convert the parallel bits into an output analog signal that is representative of the digital input signal. The neural network may be hardwired and the synapses may rely on memristors as programmable elements.

Abstract: A pipelined ADC system comprising: a first ADC stage comprising a trainable neural network layer and configured to receive an analog input signal, and convert it into a first n-bit digital output representing said analog input signal; a DAC circuit comprising a trainable neural network layer and configured to receive said first n-bit digital output, and convert it into an analog output signal representing said first n-bit digital output; and a second ADC stage comprising a trainable neural network layer and configured to receive a residue analog input signal of said analog input signal, and convert it into a second n-bit digital output representing said residue analog input signal; wherein said first and second n-bit digital outputs are combined to generate a combined digital output representing said analog input signal.

Abstract: A neural network comprising: a plurality of interconnected neural network elements, each comprising: a neuron circuit comprising a delta-sigma modulator, and at least one synapse device comprising a memristor connected to an output of said neuron circuit; wherein an adjustable synaptic weighting of said at least one synapse device is set based on said output of said neuron circuit

Abstract: A pipelined ADC system comprising: a first ADC stage comprising a trainable neural network layer and configured to receive an analog input signal, and convert it into a first n-bit digital output representing said analog input signal; a DAC circuit comprising a trainable neural network layer and configured to receive said first n-bit digital output, and convert it into an analog output signal representing said first n-bit digital output; and a second ADC stage comprising a trainable neural network layer and configured to receive a residue analog input signal of said analog input signal, and convert it into a second n-bit digital output representing said residue analog input signal; wherein said first and second n-bit digital outputs are combined to generate a combined digital output representing said analog input signal.

Abstract: A digital to analog converter is constructed using a neural network layer. The converter has inputs for receiving parallel bits of a digital input signal and an output for outputting an analog signal which is based on the digital input. Connecting the input and the output is a neural network layer which is configured to convert the parallel bits into an output analog signal that is representative of the digital input signal. The neural network may be hardwired and the synapses may rely on memristors as programmable elements.

Abstract: An analog to digital converter comprises an input for receiving an analog input signal; a plurality of outputs for outputting parallel bits of a digital signal that represents said analog input signal; and a neural network layer providing connections between each of said outputs respectively, each connection having an adjustable weighting. The synapses of the neural networks may be memristors and training may use online gradient descent.

Abstract: An analog signal processing circuit comprising: a first promoter operably linked to a nucleic acid sequence encoding a first output molecule, wherein said promoter is responsive to a cooperative input signal comprising at least two cooperative inputs, and wherein expression of said at least two cooperative inputs is tunable.