Abstract: Ping-pong readout architecture allows for faster frame rates in CMOS image sensors. However, various problems are created by this architecture due to cross-talk between components. Provided herein are novel ping-pong readout layouts which better isolate components to reduce crosstalk issues. Also provided herein are novel timing schemes for operating ping-pong readout circuits which prevent crosstalk signal spikes or readout corruption.

Abstract: An image sensor pixel the conformist single pixel of a larger array. The image sensor pixel can be a large one, such as larger than 100 ?m. The image sensor pixel has readout notes on multiple sides thereof, e.g. on to work for sides, that are symmetrically located on the pixel. The readout notes are simultaneously read out to read out a part of the image from the pixel.

Abstract: A stitched image sensor array on a semiconductor substrate with identical blocks that have wherein said first configuration includes enable inputs, which vary a function of the block depending on the connection to the enable inputs. The enable inputs can set an SRAM to receive different numbers of inputs.

Abstract: Ping-pong readout architecture allows for faster frame rates in CMOS image sensors. However, various problems are created by this architecture due to cross-talk between components. Provided herein are novel ping-pong readout layouts which better isolate components to reduce crosstalk issues. Also provided herein are novel timing schemes for operating ping-pong readout circuits which prevent crosstalk signal spikes or readout corruption.

Abstract: An image sensor system has a first stitched image sensor part that has multiple image sensing pixels and pixel gates. The multiple pixel gates are connected together by a first line on the first stitched image sensor part, and said multiple pixel gates are controlled by a first control signal. A second stitched image sensor part also has multiple sensing pixels and pixel gates, and the multiple pixel gates are connected together by a second line on said second stitched image sensor part, and said multiple pixel gates on said second stitched image sensor part are controlled by the first control signal. A driver for the first control signal, wherein said driver includes a first part for controlling said multiple pixel gates of said first stitched image sensor part and said driver has a second part, also driven by the same first control signal, for controlling said multiple pixel gates of said second stitched image sensor part.

Abstract: The invention comprises an improved process of reading out SRAM or like memory elements which utilize pre-charging of cell output buses. In the output configuration of the invention, Gray Code counter outputs are used as inputs in a decoder block, the decoder block being configured to output a valid column selection address for every two address inputs. These column outputs are mapped sequentially to the columns of the memory array, such that the columns are sequentially read out, each readout operation being interspersed with a parking interval. The Gray code address inputs reduce readout addressing errors and the parking interval creates a delay between cell readout operations that reduces glitch errors.

Abstract: An image sensor system using a circuit that automatically provides a multiple point output which represents, in a first mode, each of the multiple points receiving outputs at substantially the same time delayed only by a transit time across a wire connecting the multiple point outputs, and in a second mode, each of the multiple points producing outputs that are delayed by a delay time, where each output is delayed relative to each other output by said delay time in the second mode.

Abstract: Calibrating of A/D converters is carried out by obtaining adjustable reference voltages which are used in A/D conversion, comparing a first divided reference voltage of a full range voltage Vref, with a second divided reference voltage of Vref using analog to digital converters that are used in the A/D conversion; and adjusting at least one of said reference voltages to obtain a set ratio between said multiple ones of said reference voltages. The compared values can include a divided version of Vref, e.g., 3/8 Vref.

Abstract: An image sensor system using a circuit that automatically provides a multiple point output which represents, in a first mode, each of the multiple points receiving outputs at substantially the same time delayed only by a transit time across a wire connecting the multiple point outputs, and in a second mode, each of the multiple points producing outputs that are delayed by a delay time, where each output is delayed relative to each other output by said delay time in the second mode.

Abstract: An image sensor pixel the conformist single pixel of a larger array. The image sensor pixel can be a large one, such as larger than 100 ?m. The image sensor pixel has readout notes on multiple sides thereof, e.g. on to work for sides, that are symmetrically located on the pixel. The readout notes are simultaneously read out to read out a part of the image from the pixel.

Abstract: A stitched image sensor array on a semiconductor substrate with identical blocks that have wherein said first configuration includes enable inputs, which vary a function of the block depending on the connection to the enable inputs. The enable inputs can set an SRAM to receive different numbers of inputs.

Abstract: Calibrating of A/D converters is carried out by obtaining adjustable reference voltages which are used in in A/D conversion, comparing a first divided reference voltage of a full range voltage Vref, with a second divided reference voltage of Vref using analog to digital converters that are used in the A/D conversion; and adjusting at least one of said reference voltages to obtain a set ratio between said multiple ones of said reference voltages. The compared values can include a divided version of Vref, e.g., 3/8 Vref.

Abstract: A video system is disclosed which is capable of receiving digital data from a source such as a video camera, and subsequently transferring the received data into a main frame buffer for display on a video display, where the data from the source can overlay a primary image stored in the main frame buffer. An auxiliary frame buffer, consisting of a bank of dual-port RAMs, receives the data of the overlay image via its serial port and transfers this data into the randomly accessible array therein. A direct-memory-access (DMA) operation performs the transfer from the auxiliary frame buffer into the main frame buffer, with the source and destination positions in the auxiliary and main frame buffers, respectively, independently selectable. The performance of the DMA operation can be enhanced by simultaneously performing a page mode read of the auxiliary frame buffer with a page mode write to the main frame buffer.

Abstract: A video system is disclosed which is capable of receiving digital data from a source such as a video camera, and subsequently transferring the received data into a main frame buffer for display on a video display, where the data from the source can overlay a primary image stored in the main frame buffer. An auxiliary frame buffer, consisting of a bank of dual-port RAMs, receives the data of the overlay image via its serial port and transfers this data into the randomly accessible array therein. A direct-memory-access (DMA) operation performs the transfer from the auxiliary frame buffer into the main frame buffer, with the source and destination positions in the auxiliary and main frame buffers, respectively, independently selectable. The performance of the DMA operation can be enhanced by simultaneously performing a page mode read of the auxiliary frame buffer with a page mode write to the main frame buffer.

Abstract: The overlaying of video image data from an external source, such as a video camera, onto a representation of display data becomes accomplished by using a serial port of an auxiliary frame buffer to receive the serial data from the external source. The source data then becomes transferred from serial registers included within the auxiliary frame buffer into the randomly accessible array of the auxiliary frame buffer. Subsequent execution of a DMA (Direct Memory Access) places the source data overlaid into the image data in the master frame buffer for communication to the video display. Separate designation of the memory address in the auxiliary frame buffer and the main frame buffer allow the overlaying of data from the auxiliary frame buffer into the main frame buffer asynchronously or in a manner not requiring synchronization of the displayed positions relative to one another.