Patents by Inventor Loganathan Lingappan

Loganathan Lingappan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHODS AND APPARATUS TO GENERATE SEMICONDUCTOR PRODUCT YIELD INDICATORS
    Publication number: 20250272222
    Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to generate semiconductor product yield indicators. Examples disclosed herein are to cause at least one processor circuit to encode a data string to represent a sequence of test results corresponding to a plurality of test instances performed by automated test equipment on a first device under test. Disclosed examples are also to cause the at least one processor circuit to output the data string to a second device.
    Type: Application
    Filed: February 28, 2024
    Publication date: August 28, 2025
    Inventors: Abhinav Chandola, Loganathan Lingappan, Jason Barry Laderman-Jones, Lance Christian Cheney, Patrick Ryan McKinney, John Wayne Cagle, JR., Timothy Kirkham, John Chhokar, Haritha Mogilisetti, Stephen Francis Herndon, Jason D. McDaniel, Michael Vladimirsky, Fayez Abu-Ghosh, Beena Roshini John William, Puja Sharma
  • System-level test architecture for delivery of compressed tests
    Patent number: 7278123
    Abstract: An integrated circuit comprising at least one system level decompressor and at least a first hardware block associated with a core level decompressor. The system level decompressor is capable of performing system level decompression of received compressed test data to form partially decompressed test data. The core level decompressor being capable of performing core level decompression of the partially decompressed test data.
    Type: Grant
    Filed: March 9, 2004
    Date of Patent: October 2, 2007
    Assignee: NEC Laboratories America, Inc.
    Inventors: Srivaths Ravi, Anand Raghunathan, Loganathan Lingappan, Srimat Chakradhar, Niraj K Jha
  • System-level test architecture for delivery of compressed tests
    Publication number: 20050097413
    Abstract: An integrated circuit comprising at least one system level decompressor and at least a first hardware block associated with a core level decompressor. The system level decompressor is capable of performing system level decompression of received compressed test data to form partially decompressed test data. The core level decompressor being capable of performing core level decompression of the partially decompressed test data.
    Type: Application
    Filed: March 9, 2004
    Publication date: May 5, 2005
    Inventors: Srivaths Ravi, Anand Raghunathan, Loganathan Lingappan, Srimat Chakradhar, Niraj Jha