Patents by Inventor Loh Choong KEAT

Loh Choong KEAT has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Chip scale package semiconductor device and method of manufacture
    Patent number: 11817360
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device. The chip scale package semiconductor device comprises: a semiconductor die having a first major surface and an opposing second major surface, the semiconductor die comprising at least two terminals arranged on the second major surface; a carrier comprising a first major surface and an opposing second major surface, wherein the first major surface of the semiconductor die is mounted on the opposing second major surface of the carrier; and a molding material partially encapsulating the semiconductor die and the carrier, wherein the first major surface of the carrier extends and is exposed through molding material, and the at least two terminals are exposed through molding material on a second side of the device.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: November 14, 2023
    Assignee: Nexperia B.V.
    Inventors: Loh Choong Keat, Edward Then, Weng Khoon Mong
  • CHIP SCALE PACKAGE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE
    Publication number: 20190189530
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device. The chip scale package semiconductor device comprises: a semiconductor die having a first major surface and an opposing second major surface, the semiconductor die comprising at least two terminals arranged on the second major surface; a carrier comprising a first major surface and an opposing second major surface, wherein the first major surface of the semiconductor die is mounted on the opposing second major surface of the carrier; and a molding material partially encapsulating the semiconductor die and the carrier, wherein the first major surface of the carrier extends and is exposed through molding material, and the at least two terminals are exposed through molding material on a second side of the device.
    Type: Application
    Filed: December 14, 2018
    Publication date: June 20, 2019
    Applicant: NEXPERIA B.V.
    Inventors: Loh Choong KEAT, Edward THEN, Weng Khoon MONG