Patents by Inventor Lohit Yerva

Lohit Yerva has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11954360
    Abstract: Systems, apparatuses and methods may provide for technology that programs a plurality of seed values into a plurality of linear feedback shift registers (LFSRs), wherein the plurality of LFSRs correspond to a data word (DWORD) and at least two of the plurality of seed values differ from one another. The technology may also train a link coupled to the plurality of LFSRs, wherein the plurality of seed values cause a parity bit associated with the DWORD to toggle while the link is being trained. In one example, the technology also automatically selects the plurality of seed values based on one or more of an expected traffic pattern on the link (e.g., after training) or a deskew constraint associated with the link.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: April 9, 2024
    Assignee: Intel Corporation
    Inventors: Narasimha Lanka, Kuljit Bains, Lohit Yerva
  • Publication number: 20220358061
    Abstract: In a memory subsystem, a physical interface (PHY) has an unmatched architecture. To compensate for the unmatched architecture, the PHY has variable delay compensation to adjust for propagation mismatch of analog signals in the data (DQ) path and data strobe (DQS) path of the PHY. The variable delay compensation can be provided by adjusting the operation of a digital component of the PHY to introduce the delay compensation.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 10, 2022
    Inventors: Jai Ram SILIVERI, Pooja K. JADHAV, Sampath DAKSHINAMURTHY, Mohammad M. RASHID, Lohit YERVA
  • Publication number: 20210225827
    Abstract: A multi-chip device having a configurable physical interface in a logic die to on-package memory is provided. The configurable physical interface to allow a connection from a signal on the memory interface to be selected based on whether the logic die is mirrored or non-mirrored.
    Type: Application
    Filed: March 26, 2021
    Publication date: July 22, 2021
    Inventors: Narasimha LANKA, Lohit YERVA, Mohammad RASHID, Kuljit S. BAINS
  • Publication number: 20200393997
    Abstract: Systems, apparatuses and methods may provide for technology that programs a plurality of seed values into a plurality of linear feedback shift registers (LFSRs), wherein the plurality of LFSRs correspond to a data word (DWORD) and at least two of the plurality of seed values differ from one another. The technology may also train a link coupled to the plurality of LFSRs, wherein the plurality of seed values cause a parity bit associated with the DWORD to toggle while the link is being trained. In one example, the technology also automatically selects the plurality of seed values based on one or more of an expected traffic pattern on the link (e.g., after training) or a deskew constraint associated with the link.
    Type: Application
    Filed: September 1, 2020
    Publication date: December 17, 2020
    Inventors: Narasimha Lanka, Kuljit Bains, Lohit Yerva