Patents by Inventor loi Lam

loi Lam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250125582
    Abstract: An integrated device for optical power control and stabilization is provided. The integrated device includes a laser source and an optical amplifier operably coupled to the laser source. The laser source emits a light having a narrow optical linewidth at an initial output power. The optical amplifier, for example, a semiconductor optical amplifier, receives and amplifies the light from the laser source, and emits the amplified light. The optical amplifier controls a resultant output power of the emitted amplified light to a configurable level while maintaining the narrow optical linewidth in the emitted amplified light and a lasing wavelength of the laser source constant. Based on operation with a reverse bias, the optical amplifier also operates as an optical absorber and suppresses the received light having the narrow optical linewidth without requiring a change to a drive current of the laser source.
    Type: Application
    Filed: October 11, 2024
    Publication date: April 17, 2025
    Inventors: Yee Loy LAM, Huade SHU, Lay Cheng CHOO, Long Cheng KOH, Yuen Chuen CHAN
  • Publication number: 20250102733
    Abstract: A structure for, and method of, forming a first optoelectronic circuitry that generates an optical signal, a second optoelectronic circuitry that receives an optical signal, and a loopback waveguide that connects the output from the first optoelectronic circuitry to the second optoelectronic circuitry on an interposer substrate are described. The connected circuits, together comprising a photonic integrated circuit, are electrically tested using electrical signals that are provided via probing contact pads on the PIC die. Electrical activation of the optoelectrical sending devices and the subsequent detection and measurement of the optical signals in the receiving devices, in embodiments, provides information on the operability or functionality of the PIC on the die at the wafer level, prior to die separation or singulation, using the electrical and optical components of the PIC circuit.
    Type: Application
    Filed: December 9, 2024
    Publication date: March 27, 2025
    Inventors: Suresh Venkatesan, Yee Loy Lam
  • Publication number: 20250012972
    Abstract: An optical subassembly includes a planar dielectric waveguide structure that is deposited at temperatures below 400 C. The waveguide provides low film stress and low optical signal loss. Optical and electrical devices mounted onto the subassembly are aligned to planar optical waveguides using alignment marks and stops. Optical signals are delivered to the submount assembly via optical fibers. The dielectric stack structure used to fabricate the waveguide provides cavity walls that produce a cavity, within which optical, optoelectronic, and electronic devices can be mounted. The dielectric stack is deposited on an interconnect layer on a substrate, and the intermetal dielectric can contain thermally conductive dielectric layers to provide pathways for heat dissipation from heat generating optoelectronic devices such as lasers.
    Type: Application
    Filed: September 20, 2024
    Publication date: January 9, 2025
    Inventors: Suresh Venkatesan, Yee Loy Lam
  • Patent number: 12174421
    Abstract: A structure for, and method of, forming a first optoelectronic circuitry that generates an optical signal, a second optoelectronic circuitry that receives an optical signal, and a loopback waveguide that connects the output from the first optoelectronic circuitry to the second optoelectronic circuitry on an interposer substrate are described. The connected circuits, together comprising a photonic integrated circuit, are electrically tested using electrical signals that are provided via probing contact pads on the PIC die. Electrical activation of the optoelectrical sending devices and the subsequent detection and measurement of the optical signals in the receiving devices, in embodiments, provides information on the operability or functionality of the PIC on the die at the wafer level, prior to die separation or singulation, using the electrical and optical components of the PIC circuit.
    Type: Grant
    Filed: March 6, 2023
    Date of Patent: December 24, 2024
    Assignee: POET Technologies, Inc.
    Inventors: Suresh Venkatesan, Yee Loy Lam
  • Patent number: 12164148
    Abstract: A structure for, and method of, forming a first optoelectronic circuitry that generates an optical signal, a second optoelectronic circuitry that receives an optical signal, and a loopback waveguide that connects the output from the first optoelectronic circuitry to the second optoelectronic circuitry on an interposer substrate are described. The connected circuits, together comprising a photonic integrated circuit, are electrically tested using electrical signals that are provided via probing contact pads on the PIC die. Electrical activation of the optoelectrical sending devices and the subsequent detection and measurement of the optical signals in the receiving devices, in embodiments, provides information on the operability or functionality of the PIC on the die at the wafer level, prior to die separation or singulation, using the electrical and optical components of the PIC circuit.
    Type: Grant
    Filed: March 27, 2023
    Date of Patent: December 10, 2024
    Assignee: POET Technologies, Inc.
    Inventors: Suresh Venkatesan, Yee Loy Lam
  • Patent number: 12149044
    Abstract: An optoelectronic device includes a semiconductor die that includes a substrate layer, a laser diode, first and second conducting pads, a cathode pad, an anode pad, and a passivation layer. The laser diode and the conducting pads are formed on the substrate layer. The formation of the conducting pads directly on the substrate layer offers an increased area for heat dissipation. The cathode pad is formed on the first conducting pad whereas the anode pad is formed above the second conducting pad. The passivation layer is formed above the laser diode. The attachment of the semiconductor die to a submount of the optoelectronic device occurs by way of the cathode pad and the anode pad. After the attachment, a free space is created directly between the passivation layer and the submount to reduce the impact of solder bonding stress on the laser diode.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: November 19, 2024
    Assignee: DENSELIGHT SEMICONDUCTORS PTE LTD
    Inventors: Yee Loy Lam, Hon Yuen Aaron Sim, Lay Cheng Choo, Long Cheng Koh
  • Patent number: 12099236
    Abstract: An optical subassembly includes a planar dielectric waveguide structure that is deposited at temperatures below 400 C. The waveguide provides low film stress and low optical signal loss. Optical and electrical devices mounted onto the subassembly are aligned to planar optical waveguides using alignment marks and stops. Optical signals are delivered to the submount assembly via optical fibers. The dielectric stack structure used to fabricate the waveguide provides cavity walls that produce a cavity, within which optical, optoelectronic, and electronic devices can be mounted. The dielectric stack is deposited on an interconnect layer on a substrate, and the intermetal dielectric can contain thermally conductive dielectric layers to provide pathways for heat dissipation from heat generating optoelectronic devices such as lasers.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: September 24, 2024
    Assignee: POET Technologies, Inc.
    Inventors: Suresh Venkatesan, Yee Loy Lam
  • Patent number: 12038610
    Abstract: A wafer-level optoelectronic packaging method includes fabricating a pre-singulated wafer. The pre-singulated wafer has a plurality of sub-mounts. A first sub-mount of the plurality of sub-mounts includes an optical waveguide formed on a substrate, a multi-layered sub-mount boundary wall that is formed on the optical waveguide, and a v-groove that is external to the sub-mount boundary wall. A plurality of optical dies are attached to the corresponding plurality of sub-mounts, such that each optical die is aligned to the optical waveguide of the corresponding sub-mount. A cap-wafer including a plurality of caps is attached to the pre-singulated wafer to obtain an encapsulated pre-singulated wafer. The encapsulated pre-singulated wafer is diced to obtain a plurality of optoelectronic packages. The optical waveguide of each optoelectronic package serves as an interconnection conduit between the corresponding optical die and an optical fiber placed in the corresponding v-groove.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: July 16, 2024
    Assignee: POET Technologies, Inc.
    Inventor: Yee Loy Lam
  • Patent number: 11906798
    Abstract: A method for forming hermetic seals between the cap and sub-mount for electronic and optoelectronic packages includes the formation of metal mounds on the sealing surfaces. Metal mounds, as precursors to a metal hermetic seal between the cap and sub-mount of a sub-mount assembly, facilitates the evacuation and purging of the volume created within cap and sub-mount assemblies prior to formation of the hermetic seal. The method is applied to discrete cap and sub-mount assemblies and also at the wafer level on singulated and non-singulated cap and sub-mount wafers. The method that includes the formation of the hermetic seal provides an inert environment for a plurality of electrical, optoelectrical, and optical die that are attached within an enclosed volume of the sub-mount assembly.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: February 20, 2024
    Assignee: POET Technologies, Inc.
    Inventors: Yee Loy Lam, Suresh Venkatesan, Long Cheng Koh
  • Publication number: 20230384516
    Abstract: A structure for, and method of, forming a first optoelectronic circuitry that generates an optical signal, a second optoelectronic circuitry that receives an optical signal, and a loopback waveguide that connects the output from the first optoelectronic circuitry to the second optoelectronic circuitry on an interposer substrate are described. The connected circuits, together comprising a photonic integrated circuit, are electrically tested using electrical signals that are provided via probing contact pads on the PIC die. Electrical activation of the optoelectrical sending devices and the subsequent detection and measurement of the optical signals in the receiving devices, in embodiments, provides information on the operability or functionality of the PIC on the die at the wafer level, prior to die separation or singulation, using the electrical and optical components of the PIC circuit.
    Type: Application
    Filed: March 27, 2023
    Publication date: November 30, 2023
    Inventors: Suresh Venkatesan, Yee Loy Lam
  • Publication number: 20230384515
    Abstract: A structure for, and method of, forming a first optoelectronic circuitry that generates an optical signal, a second optoelectronic circuitry that receives an optical signal, and a loopback waveguide that connects the output from the first optoelectronic circuitry to the second optoelectronic circuitry on an interposer substrate are described. The connected circuits, together comprising a photonic integrated circuit, are electrically tested using electrical signals that are provided via probing contact pads on the PIC die. Electrical activation of the optoelectrical sending devices and the subsequent detection and measurement of the optical signals in the receiving devices, in embodiments, provides information on the operability or functionality of the PIC on the die at the wafer level, prior to die separation or singulation, using the electrical and optical components of the PIC circuit.
    Type: Application
    Filed: March 6, 2023
    Publication date: November 30, 2023
    Inventors: Suresh Venkatesan, Yee Loy Lam
  • Patent number: 11725942
    Abstract: A photonic integrated chip is configured as a transmitter-receiver chip. The photonic integrated chip includes a light emitter, a light detector, a multi-mode interference coupler, and a mode-filed adapter. The light emitted by the light emitter is guided to a core layer formed below the multi-mode interference coupler, and further to the mode-filed adapter for transmission of light to an optical fiber coupled with the photonic integrated chip. Similarly, light received by the mode-filed adapter from the optical fiber propagates to the core layer, and is guided by the multi-mode interference coupler into the light detector. The photonic integrated chip is utilized to realize a single-unit transmitter-receiver module for a fiber optic gyroscope circuit based on monolithic integration of photonics components via wafer fabrication on a substrate. The photonic integrated chip has a low fabrication cost, low size, and is robust.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: August 15, 2023
    Assignee: DENSELIGHT SEMICONDUCTORS PTE LTD
    Inventors: Yee Loy Lam, Ter Hoe Loh, Kamal Kader, Long Cheng Koh
  • Patent number: 11614584
    Abstract: A structure for, and method of, forming a first optoelectronic circuitry that generates an optical signal, a second optoelectronic circuitry that receives an optical signal, and a loopback waveguide that connects the output from the first optoelectronic circuitry to the second optoelectronic circuitry on an interposer substrate are described. The connected circuits, together comprising a photonic integrated circuit, are electrically tested using electrical signals that are provided via probing contact pads on the PIC die. Electrical activation of the optoelectrical sending devices and the subsequent detection and measurement of the optical signals in the receiving devices, in embodiments, provides information on the operability or functionality of the PIC on the die at the wafer level, prior to die separation or singulation, using the electrical and optical components of the PIC circuit.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: March 28, 2023
    Inventors: Suresh Venkatesan, Yee Loy Lam
  • Patent number: 11598918
    Abstract: A structure for, and method of, forming a first optoelectronic circuitry that generates an optical signal, a second optoelectronic circuitry that receives an optical signal, and a loopback waveguide that connects the output from the first optoelectronic circuitry to the second optoelectronic circuitry on an interposer substrate are described. The connected circuits, together comprising a photonic integrated circuit, are electrically tested using electrical signals that are provided via probing contact pads on the PIC die. Electrical activation of the optoelectrical sending devices and the subsequent detection and measurement of the optical signals in the receiving devices, in embodiments, provides information on the operability or functionality of the PIC on the die at the wafer level, prior to die separation or singulation, using the electrical and optical components of the PIC circuit.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: March 7, 2023
    Inventors: Suresh Venkatesan, Yee Loy Lam
  • Publication number: 20230038028
    Abstract: An optical subassembly includes a planar dielectric waveguide structure that is deposited at temperatures below 400 C. The waveguide provides low film stress and low optical signal loss. Optical and electrical devices mounted onto the subassembly are aligned to planar optical waveguides using alignment marks and stops. Optical signals are delivered to the submount assembly via optical fibers. The dielectric stack structure used to fabricate the waveguide provides cavity walls that produce a cavity, within which optical, optoelectronic, and electronic devices can be mounted. The dielectric stack is deposited on an interconnect layer on a substrate, and the intermetal dielectric can contain thermally conductive dielectric layers to provide pathways for heat dissipation from heat generating optoelectronic devices such as lasers.
    Type: Application
    Filed: August 22, 2022
    Publication date: February 9, 2023
    Inventors: Suresh Venkatesan, Yee Loy Lam
  • Publication number: 20230043322
    Abstract: A mode field adapter (MFA) is disclosed. The MFA is tapered and includes a passive core region and an active core region separated by a distance. Further, the passive core region includes first and second passive layers that are separated by another distance. The MFA is configured to receive an optical signal from a first waveguide, and alter, for transmission to a second waveguide, an optical mode of the optical signal. The optical mode is altered based on the distance between the first and second passive layers, the distance between the active and passive core regions, and the tapering of the MFA. The optical mode is altered such that an optical loss associated with the optical signal traversing from the first waveguide to the second waveguide by way of the MFA is within a tolerance limit.
    Type: Application
    Filed: August 4, 2022
    Publication date: February 9, 2023
    Applicant: DENSELIGHT SEMICONDUCTORS PTE LTD
    Inventors: Ter Hoe Loh, Yee Loy Lam
  • Publication number: 20230021029
    Abstract: A wafer-level optoelectronic packaging method includes fabricating a pre-singulated wafer. The pre-singulated wafer has a plurality of sub-mounts. A first sub-mount of the plurality of sub-mounts includes an optical waveguide formed on a substrate, a multi-layered sub-mount boundary wall that is formed on the optical waveguide, and a v-groove that is external to the sub-mount boundary wall. A plurality of optical dies are attached to the corresponding plurality of sub-mounts, such that each optical die is aligned to the optical waveguide of the corresponding sub-mount. A cap-wafer including a plurality of caps is attached to the pre-singulated wafer to obtain an encapsulated pre-singulated wafer. The encapsulated pre-singulated wafer is diced to obtain a plurality of optoelectronic packages. The optical waveguide of each optoelectronic package serves as an interconnection conduit between the corresponding optical die and an optical fiber placed in the corresponding v-groove.
    Type: Application
    Filed: September 19, 2022
    Publication date: January 19, 2023
    Inventor: Yee Loy LAM
  • Patent number: 11531160
    Abstract: An optical subassembly includes a planar dielectric waveguide structure that is deposited at temperatures below 400 C. The waveguide provides low film stress and low optical signal loss. Optical and electrical devices mounted onto the subassembly are aligned to planar optical waveguides using alignment marks and stops. Optical signals are delivered to the submount assembly via optical fibers. The dielectric stack structure used to fabricate the waveguide provides cavity walls that produce a cavity, within which optical, optoelectronic, and electronic devices can be mounted. The dielectric stack is deposited on an interconnect layer on a substrate, and the intermetal dielectric can contain thermally conductive dielectric layers to provide pathways for heat dissipation from heat generating optoelectronic devices such as lasers.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: December 20, 2022
    Inventors: Suresh Venkatesan, Yee Loy Lam
  • Publication number: 20220329045
    Abstract: A laser module includes a gain chip, temperature sensors, a case, and a thermoelectric cooler (TEC). The gain chip emits a laser beam. One of the temperature sensors measures a first temperature of the gain chip and is encompassed by the gain chip. The other temperature sensor is adhered to the case and measures a second temperature. The TEC tunes the laser beam emitted by the gain chip to a desired wavelength by varying the first temperature of the gain chip through a set of third temperatures for various values of the second temperature. The set of third temperatures is selected from various values of the first temperature such that the laser beam emitted at the set of third temperatures is mode-hop free.
    Type: Application
    Filed: March 24, 2022
    Publication date: October 13, 2022
    Applicant: DENSELIGHT SEMICONDUCTORS PTE LTD
    Inventors: Kamal Kader, Long Cheng Koh, Andy Piper, Yee Loy Lam
  • Patent number: 11448827
    Abstract: A wafer-level optoelectronic packaging method includes fabricating a pre-singulated wafer. The pre-singulated wafer has a plurality of sub-mounts. A first sub-mount of the plurality of sub-mounts includes an optical waveguide formed on a substrate, a multi-layered sub-mount boundary wall that is formed on the optical waveguide, and a v-groove that is external to the sub-mount boundary wall. A plurality of optical dies are attached to the corresponding plurality of sub-mounts, such that each optical die is aligned to the optical waveguide of the corresponding sub-mount. A cap-wafer including a plurality of caps is attached to the pre-singulated wafer to obtain an encapsulated pre-singulated wafer. The encapsulated pre-singulated wafer is diced to obtain a plurality of optoelectronic packages. The optical waveguide of each optoelectronic package serves as an interconnection conduit between the corresponding optical die and an optical fiber placed in the corresponding v-groove.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: September 20, 2022
    Assignee: POET Technologies, Inc.
    Inventor: Yee Loy Lam