Patents by Inventor Loic Gaben
Loic Gaben has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11515148Abstract: Method for producing a semiconductor device, including: producing, on a first region of a surface layer comprising a first semiconductor and disposed on a buried dielectric layer, a layer of a second compressive strained semiconductor along a first direction; etching a trench through the layer of the second semiconductor forming an edge of a portion of the layer of the second semiconductor oriented perpendicularly to the first direction, and wherein the bottom wall is formed by the surface layer; thermal oxidation forming in the surface layer a semiconductor compressive strained portion along the first direction and forming in the trench an oxide portion; producing, through the surface layer and/or the oxide portion, and through the buried dielectric layer, dielectric isolation portions around an assembly formed of the compressive strained semiconductor portion and the oxide portion; and wherein the first semiconductor is silicon, the second semiconductor is SiGe, and said at least one compressive strainedType: GrantFiled: June 29, 2020Date of Patent: November 29, 2022Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Loic Gaben, Cyrille Le Royer, Fabrice Nemouchi, Nicolas Posseme, Shay Reboh
-
Patent number: 11217446Abstract: A process for fabricating an integrated circuit is provided, including steps of providing a substrate including a silicon layer, a layer of insulator a layer of hard mask and accesses to first and second regions of the silicon layer; forming first and second deposits of SiGe alloy on the first and the second regions in order to form first and second stacks; then protecting the first deposit and maintaining an access to the second deposit; then performing an etch in order to form trenches between the hard mask and two opposite edges of the second stack; then forming a tensilely strained silicon layer in the second region via amorphization of the second region; then crystallization; and enriching the first region in germanium by diffusion from the first deposit.Type: GrantFiled: December 17, 2019Date of Patent: January 4, 2022Assignee: Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Nicolas Posseme, Loic Gaben, Cyrille Le Royer, Fabrice Nemouchi, Shay Reboh
-
Patent number: 10998236Abstract: A strip made of a semiconductor material is formed over a substrate. Longitudinal portions of the strip having a same length are covered with sacrificial gates made of an insulating material and spaced apart from each other. Non-covered portions of the strip are doped to form source/drain regions. An insulating layer followed by a layer of a temporary material is then deposited. Certain ones of the sacrificial gates are left in place. Certain other ones of the sacrificial gates are replaced by a metal gate structure. The temporary material is then replaced with a conductive material to form contacts to the source/drain regions.Type: GrantFiled: September 25, 2019Date of Patent: May 4, 2021Assignee: STMicroelectronics (Crolles 2) SASInventor: Loic Gaben
-
Publication number: 20210005443Abstract: Method for producing a semiconductor device, including: producing, on a first region of a surface layer comprising a first semiconductor and disposed on a buried dielectric layer, a layer of a second compressive strained semiconductor along a first direction; etching a trench through the layer of the second semiconductor forming an edge of a portion of the layer of the second semiconductor oriented perpendicularly to the first direction, and wherein the bottom wall is formed by the surface layer; thermal oxidation forming in the surface layer a semiconductor compressive strained portion along the first direction and forming in the trench an oxide portion; producing, through the surface layer and/or the oxide portion, and through the buried dielectric layer, dielectric isolation portions around an assembly formed of the compressive strained semiconductor portion and the oxide portion; and wherein the first semiconductor is silicon, the second semiconductor is SiGe, and said at least one compressive strainedType: ApplicationFiled: June 29, 2020Publication date: January 7, 2021Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Loic GABEN, Cyrille LE ROYER, Fabrice NEMOUCHI, Nicolas POSSEME, Shay REBOH
-
Patent number: 10804112Abstract: A planarization structure is formed with a planar upper face enclosing a relief projecting from a planar substrate. The process used deposits a layer of a first material over the reliefs and then forms a layer of a second material with a planar upper face. This second material may be etched selectively with respect to the first material. The second layer is processed so that the protuberances of the first material are uncovered. A planarizing is then performed on the first material as far as the layer of the second material by selective chemical-mechanical polishing with respect to the second material.Type: GrantFiled: May 14, 2018Date of Patent: October 13, 2020Assignee: STMicroelectronics (Crolles 2) SASInventor: Loic Gaben
-
Publication number: 20200203161Abstract: A process for fabricating an integrated circuit is provided, including steps of providing a substrate including a silicon layer, a layer of insulator a layer of hard mask and accesses to first and second regions of the silicon layer; forming first and second deposits of SiGe alloy on the first and the second regions in order to form first and second stacks; then protecting the first deposit and maintaining an access to the second deposit; then performing an etch in order to form trenches between the hard mask and two opposite edges of the second stack; then forming a tensilely strained silicon layer in the second region via amorphization of the second region; then crystallization; and enriching the first region in germanium by diffusion from the first deposit.Type: ApplicationFiled: December 17, 2019Publication date: June 25, 2020Applicant: Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Nicolas POSSEME, Loic Gaben, Cyrille Le Royer, Fabrice Nemouchi, Shay Reboh
-
Publication number: 20200020589Abstract: A strip made of a semiconductor material is formed over a substrate. Longitudinal portions of the strip having a same length are covered with sacrificial gates made of an insulating material and spaced apart from each other. Non-covered portions of the strip are doped to form source/drain regions. An insulating layer followed by a layer of a temporary material is then deposited. Certain ones of the sacrificial gates are left in place. Certain other ones of the sacrificial gates are replaced by a metal gate structure. The temporary material is then replaced with a conductive material to form contacts to the source/drain regions.Type: ApplicationFiled: September 25, 2019Publication date: January 16, 2020Applicant: STMicroelectronics (Crolles 2) SASInventor: Loic GABEN
-
Patent number: 10483154Abstract: In various aspects, the present disclosure relates to device structures and a method of forming such a device structure. In some illustrative embodiments herein, a device is provided, including a semiconductor substrate having a first trench formed therein, and a first trench isolation structure formed in the first trench. The first trench isolation structure includes first and second insulating liners formed adjacent inner surfaces of the first trench, wherein the first insulating liner is in direct contact with inner surfaces of the first trench and the second insulating liner is formed directly on the first insulating liner, and a first insulating filling material which at least partially fills the first trench. In some aspects, a thickness of the first insulating liner is greater than a thickness of the second insulating liner.Type: GrantFiled: June 22, 2018Date of Patent: November 19, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Elliot John Smith, Marcus Wolf, Carsten Peters, Markus Lenski, Loic Gaben
-
Patent number: 10468306Abstract: A strip made of a semiconductor material is formed over a substrate. Longitudinal portions of the strip having a same length are covered with sacrificial gates made of an insulating material and spaced apart from each other. Non-covered portions of the strip are doped to form source/drain regions. An insulating layer followed by a layer of a temporary material is then deposited. Certain ones of the sacrificial gates are left in place. Certain other ones of the sacrificial gates are replaced by a metal gate structure. The temporary material is then replaced with a conductive material to form contacts to the source/drain regions.Type: GrantFiled: April 1, 2018Date of Patent: November 5, 2019Assignee: STMicroelectronics (Crolles 2) SASInventor: Loic Gaben
-
Publication number: 20180330961Abstract: A planarization structure is formed with a planar upper face enclosing a relief projecting from a planar substrate. The process used deposits a layer of a first material over the reliefs and then forms a layer of a second material with a planar upper face. This second material may be etched selectively with respect to the first material. The second layer is processed so that the protuberances of the first material are uncovered. A planarizing is then performed on the first material as far as the layer of the second material by selective chemical-mechanical polishing with respect to the second material.Type: ApplicationFiled: May 14, 2018Publication date: November 15, 2018Applicant: STMicroelectronics (Crolles 2) SASInventor: Loic GABEN
-
Publication number: 20180330998Abstract: A strip or portions of a strip of silicon-germanium is made by first producing a strip of silicon suspended above a substrate. At least a portion of the strip of silicon is with a layer of silicon-germanium. Germanium enrichment of the portion of the strip of silicon is accomplished through a thermal oxidation. The resulting silicon oxide formed during the thermal oxidation is then removed.Type: ApplicationFiled: May 8, 2018Publication date: November 15, 2018Applicant: STMicroelectronics (Crolles 2) SASInventor: Loic GABEN
-
Publication number: 20180286763Abstract: A strip made of a semiconductor material is formed over a substrate. Longitudinal portions of the strip having a same length are covered with sacrificial gates made of an insulating material and spaced apart from each other. Non-covered portions of the strip are doped to form source/drain regions. An insulating layer followed by a layer of a temporary material is then deposited. Certain ones of the sacrificial gates are left in place. Certain other ones of the sacrificial gates are replaced by a metal gate structure. The temporary material is then replaced with a conductive material to form contacts to the source/drain regions.Type: ApplicationFiled: April 1, 2018Publication date: October 4, 2018Applicant: STMicroelectronics (Crolles 2) SASInventor: Loic GABEN
-
Patent number: 10026821Abstract: An all-around gate field-effect transistor includes two drain-source areas supported by a semiconductor substrate. At least one channel region, surrounded with a gate insulated by a gate insulator, extends between the two drain-source areas. The at least one channel region is located above an insulating layer resting on the substrate and positioned between the two drain-source areas. This insulating layer has a thickness-to-permittivity ratio at least 2 times greater than that of the gate insulator. An extension of the insulating layer is positioned to insulate at least one of the channel regions from the semiconductor substrate.Type: GrantFiled: March 23, 2017Date of Patent: July 17, 2018Assignee: STMicroelectronics (Crolles 2) SASInventor: Loic Gaben
-
Publication number: 20180061955Abstract: An all-around gate field-effect transistor includes two drain-source areas supported by a semiconductor substrate. At least one channel region, surrounded with a gate insulated by a gate insulator, extends between the two drain-source areas. The at least one channel region is located above an insulating layer resting on the substrate and positioned between the two drain-source areas. This insulating layer has a thickness-to-permittivity ratio at least 2 times greater than that of the gate insulator. An extension of the insulating layer is positioned to insulate at least one of the channel regions from the semiconductor substrate.Type: ApplicationFiled: March 23, 2017Publication date: March 1, 2018Applicant: STMicroelectronics (Crolles 2) SASInventor: Loic Gaben