Abstract: A method is described for addressing units (FU1, FU2, FU3) amongst a plurality of units having different addresses (ADD1, ADD2, ADD3) by use of an address word (AW), the addresses and the address word being composed of address elements. A tag word (TW) is transmitted to the plurality of units, the tag word defining which address elements of the address word are significant (S) and which address elements of the address word are non significant (X). The address word and the addresses of the units are compared and, a unit is addressed if the significant elements of the address word match the corresponding elements of the unit's address.

Abstract: A data processing arrangement comprises various data processors (P) and a memory arrangement (MA) for supplying input data (Di) to the data processors (P) and for storing output data (Do) from the data processors (P). The following steps are alternately carried out: a configuring step (CS) and a processing step (PS). In a configuration step (CS), the data processing arrangement is configured such that each data processor (P) will process a block (B) of data contained in the memory arrangement (MA) and then stop processing data. In a processing step (PS), the blocks (B) of data are processed in the respective data processors (P). A subsequent configuring step (CS) is carried out only when each data processor (P) has processed its block (B) of data (∀P: B=PROC>CS). Such a data processing arrangement allows great versatility because different data processing chains can be realized without this requiring relatively complicated software.