Abstract: Programmable devices and methods of programming programmable devices are described. In one embodiment, a complex programmable logic device (CPLD) is programmed by a remote host programming unit that provides the configuration data over a data communications link into a first data-holding location on the device all at one time. The device is then locally programmed under the influence of a controller that causes the configuration data in the first data-holding location to be written or copied to a second data-holding location on the device. In one embodiment, the first data-holding location is a rapidly programmed temporary memory (e.g., RAM), while the second data-holding location is a non-volatile memory that takes much longer to program (e.g., EEPROM or flash memory) and actually controls the device functionality. This technique frees up the host programming unit and the data communications link to attend to other matters, such as providing configuration data to other programmable devices.

Abstract: A self-addressing memory device is provided that can provide blocks of data starting from more than one initial location in the device, and may have the option of reading in either direction. This memory device can efficiently store multiple bitstreams, which may be of different sizes, that are used to configure one or more configurable logic devices. Each stored bitstream can be accessed in any order. In one embodiment, the configurable logic device is a Field Programmable Gate Array ("FPGA"). In one embodiment, the memory device is a Read-Only Memory ("ROM") that is either read up from all zeros or down from all ones. In one embodiment, the ROM includes a bidirectional chip enable chain that permits cascading multiple ROMs.

Abstract: A self-addressing memory device is provided that can provide blocks of data starting from more than one initial location in the device, and may have the option of reading in either direction. This memory device can efficiently store multiple bitstreams, which may be of different sizes, that are used to configure one or more configurable logic devices. Each stored bitstream can be accessed in any order. In one embodiment, the configurable logic device is a Field Programmable Gate Array ("FPGA"). In one embodiment, the memory device is a Read-Only Memory ("ROM") that is either read up from all zeros or down from all ones. In one embodiment, the ROM includes a bidirectional chip enable chain that permits cascading multiple ROMs.