Patents by Inventor Lois E. Yong

Lois E. Yong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device having a bond pad and method therefor
    Patent number: 7271013
    Abstract: A bond pad (10) has a probe region (14) and a wire bond region (12) that are substantially non-overlapping. In one embodiment, the bond pad (10) is connected to a final metal layer pad (16) and extends over an interconnect region (24). The bond pad (10) is formed from aluminum and the final metal layer pad (16) is formed from copper. Separating the probe region (14) from the wire bond region (12) prevents the final metal layer pad (16) from being damaged by probe testing, allowing for more reliable wire bonds. In another embodiment, the probe region (14) extends over a passivation layer (18). In an application requiring very fine pitch between bond pads, the probe regions (14) and wire bond regions (12) of a plurality of bond pads formed in a line may be staggered to increase the distance between the probe regions (14). In addition, forming the bond pads (10) over the interconnect region (24) reduces the size of the integrated circuit.
    Type: Grant
    Filed: December 10, 2004
    Date of Patent: September 18, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Lois E. Yong, Peter R. Harper, Tu Anh Tran, Jeffrey W. Metz, George R. Leal, Dieu Van Dinh
  • Semiconductor device having a bond pad and method therefor
    Patent number: 6844631
    Abstract: A bond pad (10) has a probe region (14) and a wire bond region (12) that are substantially non-overlapping. In one embodiment, the bond pad (10) is connected to a final metal layer pad (16) and extends over an interconnect region (24). The bond pad (10) is formed from aluminum and the final metal layer pad (16) is formed from copper. Separating the probe region (14) from the wire bond region (12) prevents the final metal layer pad (16) from being damaged by probe testing, allowing for more reliable wire bonds. In an application requiring very fine pitch between bond pads, the probe regions (14) and active regions (12) of a plurality of bond pads formed in a line may be staggered to increase the distance between the probe regions (14). In addition, forming the bond pads (10) over the interconnect region (24) reduces the size of the integrated circuit.
    Type: Grant
    Filed: March 13, 2002
    Date of Patent: January 18, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Lois E. Yong, Peter R. Harper, Tu Anh Tran, Jeffrey W. Metz, George R. Leal, Dieu Van Dinh
  • Semiconductor device having a bond pad and method therefor
    Publication number: 20030173667
    Abstract: A bond pad (10) has a probe region (14) and a wire bond region (12) that are substantially non-overlapping. In one embodiment, the bond pad (10) is connected to a final metal layer pad (16) and extends over an interconnect region (24). The bond pad (10) is formed from aluminum and the final metal layer pad (16) is formed from copper. Separating the probe region (14) from the wire bond region (12) prevents the final metal layer pad (16) from being damaged by probe testing, allowing for more reliable wire bonds. In an application requiring very fine pitch between bond pads, the probe regions (14) and active regions (12) of a plurality of bond pads formed in a line may be staggered to increase the distance between the probe regions (14). In addition, forming the bond pads (10) over the interconnect region (24) reduces the size of the integrated circuit.
    Type: Application
    Filed: March 13, 2002
    Publication date: September 18, 2003
    Inventors: Lois E. Yong, Peter R. Harper, Tu Anh Tran, Jeffrey W. Metz, George R. Leal, Dieu Van Dinh