Abstract: A control register residing in a circuit chip stores a set of hardware parameters which exercise programmable control over circuits in the chip to allow for various critical hardware options. A plurality of chips and their control registers may be addressed and written individually by a processor through normal bus access. Each control register is permitted to be written only once, shortly after reset. A circuit, in response to a reset signal and a chip select signal, enables the individual control register for writing, and further, in response to a write strobe, latches data from the data bus into the register and soon afterwards ceases enabling the register for further writes.

Abstract: A control register residing in a circuit chip stores a set of hardware parameters which exercise programmable control over circuits in the chip to allow for various critical hardware options. A plurality of chips and their control registers may be addressed and written individually by a processor through normal bus access. Each control register is permitted to be written only once, shortly after reset. A circuit, in response to a reset signal and a chip select signal, enables the individual control register for writing, and further, in response to a write strobe, latches data from the data bus into the register and soon afterwards ceases enabling the register for further writes.

Abstract: A bus-oriented integrated circuit chip containing devices such as Receive and Transmit FIFO's further includes a testing circuit for testing normally inaccessible internal nodes in a FIFO device. The testing circuit includes test mode control register for storing the externally supplied test addresses of selected internal nodes of a FIFO device. A decoder, responding to a test command from a host microprocessor, selects the test addresses from the test mode control register and supplies them instead of other addresses to an internal address bus. A test decoder responds only to the test addresses on the internal address bus for enabling the transfer of data between the selected internal nodes and a data bus, thereby enabling bus access of the normally inaccessible internal nodes of a FIFO device.

Abstract: The testing circuit for testing internal nodes of a device includes storage for storing the test addresses of selected internal nodes in the device. A decoder responds to a test command from a microprocessor for selecting the test addresses from the storage and supplies the test addresses to an address bus in place of other addresses supplied to the address bus. A test decoder responds only to the test addresses on the address bus for enabling the transfer of data between the selected internal nodes in the data bus for testing the selected internal nodes.

Abstract: The fill or empty level of a FIFO is detected and compared to a first request level for the direct memory access controller or the coprocessor. When the fill or empty level exceeds the first request level, notification to the DMA or the coprocessor is generated. The fill or empty level is also compared to a second request level and when such level exceeds second request level, notification to the CPU is generated. Thus, in most cases, the DMA or coprocessor is able to obtain control of the bus before the request level for CPU interrupt is reached, thereby preventing wasteful CPU intervention as well as FIFO overruns and underruns. In case the DMA or coprocessor is unable to obtain control of the bus before the request level for CPU interrupt is reached, CPU intervention is available as a last resort.