Patents by Inventor Loizos Efthymiou
Loizos Efthymiou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240143013Abstract: A III-nitride power semiconductor based heterojunction device comprising a substrate, a first terminal, a second terminal, a control terminal configured to receive an input switching signal during an active mode of operation and to not receive the input switching signal during a stand-by mode of operation, and an active heterojunction transistor formed on the substrate.Type: ApplicationFiled: October 31, 2022Publication date: May 2, 2024Inventors: Sheung Wai FUNG, Martin ARNOLD, Loizos EFTHYMIOU, Tara VISHIN, John William FINDLAY, Florin UDREA
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Patent number: 11955488Abstract: We disclose a III-nitride semiconductor based heterojunction power device comprising: a first heterojunction transistor formed on a substrate, the first heterojunction transistor comprising: a first III-nitride semiconductor region formed over the substrate, wherein the first III-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas; a first terminal operatively connected to the first III-nitride semiconductor region; a second terminal laterally spaced from the first terminal and operatively connected to the first III-nitride semiconductor region; a first plurality of highly doped semiconductor regions of a first polarity formed over the first III-nitride semiconductor region, the first plurality of highly doped semiconductor regions being formed between the first terminal and the second terminal; a first gate region operatively connected to the first plurality of highly doped semiconductor regions; and a second heterojunction transistor formed on thType: GrantFiled: October 31, 2022Date of Patent: April 9, 2024Assignee: CAMBRIDGE GAN DEVICES LIMITEDInventors: Florin Udrea, Loizos Efthymiou
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Patent number: 11955478Abstract: Power semiconductor devices in GaN technology include an integrated auxiliary (double) gate terminal and a pulldown network to achieve a normally-off (E-Mode) GaN transistor with threshold voltage higher than 2V, low gate leakage current and enhanced switching performance. The high threshold voltage GaN transistor has a high-voltage active GaN device and a low-voltage auxiliary GaN device wherein the high-voltage GaN device has the gate connected to the source of the integrated auxiliary low-voltage GaN transistor and the drain being the external high-voltage drain terminal and the source being the external source terminal, while the low-voltage auxiliary GaN transistor has the gate (first auxiliary electrode) connected to the drain (second auxiliary electrode) functioning as an external gate terminal.Type: GrantFiled: June 17, 2021Date of Patent: April 9, 2024Assignee: CAMBRIDGE GAN DEVICES LIMITEDInventors: Martin Arnold, Loizos Efthymiou, Florin Udrea, Giorgia Longobardi, John William Findlay
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Patent number: 11923816Abstract: An integrated circuit is provided which can sense the drain voltage of an active heterojunction transistor under different conditions and can adjust a driving signal of a gate terminal of the active heterojunction transistor in order to limit conduction losses and/or switching losses.Type: GrantFiled: January 31, 2022Date of Patent: March 5, 2024Assignee: CAMBRIDGE GAN DEVICES LIMITEDInventors: Martin Arnold, Loizos Efthymiou, Florin Udrea, John William Findlay, Giorgia Longobardi
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Patent number: 11784637Abstract: The present disclosure relates to an edge detection circuit configured to receive an input signal comprising one or more falling or falling edges and provide an output signal comprising pulses or spikes corresponding to the one or more rising or falling edges. The edge detection circuit comprises a passive differentiator circuit configured to receive an input and provide a differentiator output signal that that is proportional to the rate of change of the input, and a comparator circuit operably connected to a voltage source. The comparator circuit is configured to receive the differentiator output signal, compare the differentiator output signal to a threshold voltage; and output a pulse or spike signal based on the comparison to the threshold voltage.Type: GrantFiled: May 10, 2022Date of Patent: October 10, 2023Assignee: CAMBRIDGE GAN DEVICES LIMITEDInventors: Sheung Wai Fung, Loizos Efthymiou, Florin Udrea, Martin Arnold
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Publication number: 20230246615Abstract: We describe an integrated circuit is disclosed which can sense the drain voltage of an active heterojunction transistor under different conditions and can adjust a driving signal of a gate terminal of the active heterojunction transistor in order to limit conduction losses and/or switching losses.Type: ApplicationFiled: January 31, 2022Publication date: August 3, 2023Inventors: Martin Arnold, Loizos Efthymiou, Florin Udrea, John William Findlay, Giorgia Longobardi
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Publication number: 20230246019Abstract: We describe a heterojunction based half bridge apparatus formed within a single active area comprising a first heterojunction device and a second heterojunction device, each heterojunction device comprising a drain and a source, each drain comprising a drain contact and each source comprising a source contact; wherein the drain contact of the first heterojunction device and the source contact of the second heterojunction device comprise a common contact. The half bridge apparatus according to the present disclosure may be advantageously more compact and more reliable than existing heterojunction based half bridges.Type: ApplicationFiled: January 31, 2022Publication date: August 3, 2023Inventors: Florin Udrea, Loizos Efthymiou, Giorgia Longobardi
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Publication number: 20230246098Abstract: We describe a smart high voltage/power III-nitride semiconductor based diode or rectifier comprising first and second terminals, and further comprising an active device (e.g. a transistor such as a GaN HEMT transistor), a sensing device (e.g. a sensing diode/transistor), a sensing load (e.g. a resistor), wherein the smart high voltage/power III-nitride semiconductor based diode or rectifier is configured to output a sensing signal corresponding a current through the sensing device and/or a voltage drop across the sensing load, wherein the sensing signal is indicative of a current flowing between the first and second terminal when a bias is applied between the first and second terminals.Type: ApplicationFiled: January 31, 2022Publication date: August 3, 2023Inventors: Florin Udrea, Martin Arnold, Loizos Efthymiou, Giorgia Longobardi, Sheung Wai Fung
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Patent number: 11658236Abstract: A III-nitride semiconductor based heterojunction power device including: a first heterojunction transistor formed on a substrate, and a second heterojunction transistor formed on the substrate. One of the first heterojunction transistor and the second heterojunction transistor is an enhancement mode field effect transistor and the other one of the first heterojunction transistor and the second heterojunction transistor is a depletion mode field effect transistor. The enhancement mode transistor acts as a main power switch, and the depletion mode transistor acts as a start-up component.Type: GrantFiled: May 7, 2019Date of Patent: May 23, 2023Assignee: CAMBRIDGE GAN DEVICES LIMITEDInventors: Florin Udrea, Loizos Efthymiou, Giorgia Longobardi, Martin Arnold
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Publication number: 20230131602Abstract: A heterojunction device having at least three terminals, the at least three terminals comprising a high voltage terminal, a low voltage terminal and a control terminal. The heterojunction device further comprises at least one main power heterojunction transistor, an auxiliary gate circuit comprising at least one first low-voltage heterojunction transistor, a pull-down circuit comprising a capacitor and a charging path for the capacitor. The heterojunction device further comprises at least one monolithically integrated component, wherein the capacitor is configured to provide an internal rail voltage for the at least one monolithically integrated component.Type: ApplicationFiled: October 31, 2022Publication date: April 27, 2023Inventors: Martin ARNOLD, Sheung Wai FUNG, Loizos EFTHYMIOU, Florin UDREA, John William FINDLAY
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Publication number: 20230117946Abstract: A heterojunction device, includes a substrate (4); a Ill-nitride semiconductor region located longitudinally above or over the substrate and including a heterojunction having a two-dimensional carrier gas; first (8) and second (9) laterally spaced terminals operatively connected to the semiconductor; a gate structure (11) of first conductivity type located above or longitudinally over the semiconductor region and laterally spaced between the first and second terminals; a control gate terminal (10) operatively connected to the gate structure, a potential applied to the control gate terminal modulates and controls a current flow through the carrier gas between the terminals, the carrier gas being a second conductivity type; an injector of carriers (101) of the first conductivity type laterally spaced away from the second terminal; and a floating contact layer (102) located over the carrier gas and laterally spaced away from the second terminal and operatively connected to the injector and the semiconductor regiType: ApplicationFiled: January 13, 2021Publication date: April 20, 2023Inventors: Florin UDREA, Loizos EFTHYMIOU, Giorgia LONGOBARDI
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Publication number: 20230050918Abstract: We disclose a III-nitride semiconductor based heterojunction power device comprising: a first heterojunction transistor formed on a substrate, the first heterojunction transistor comprising: a first III-nitride semiconductor region formed over the substrate, wherein the first III-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas; a first terminal operatively connected to the first III-nitride semiconductor region; a second terminal laterally spaced from the first terminal and operatively connected to the first III-nitride semiconductor region; a first plurality of highly doped semiconductor regions of a first polarity formed over the first III-nitride semiconductor region, the first plurality of highly doped semiconductor regions being formed between the first terminal and the second terminal; a first gate region operatively connected to the first plurality of highly doped semiconductor regions; and a second heterojunction transistor formed on thType: ApplicationFiled: October 31, 2022Publication date: February 16, 2023Inventors: Florin UDREA, Loizos EFTHYMIOU
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Patent number: 11404565Abstract: The disclosure relates to power semiconductor devices in GaN technology. The disclosure proposes an integrated auxiliary (double) gate terminal and a pulldown network to achieve a normally-off (E-Mode) GaN transistor with threshold voltage higher than 2V, low gate leakage current and enhanced switching performance. The high threshold voltage GaN transistor has a high-voltage active GaN device and a low-voltage auxiliary GaN device wherein the high-voltage GaN device has the gate connected to the source of the integrated auxiliary low-voltage GaN transistor and the drain being the external high-voltage drain terminal and the source being the external source terminal, while the low-voltage auxiliary GaN transistor has the gate (first auxiliary electrode) connected to the drain (second auxiliary electrode) functioning as an external gate terminal.Type: GrantFiled: May 7, 2019Date of Patent: August 2, 2022Assignee: CAMBRIDGE ENTERPRISE LIMITEDInventors: Florin Udrea, Loizos Efthymiou, Giorgia Longobardi, Martin Arnold
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Publication number: 20220208761Abstract: We disclose a Ill-nitride semiconductor based heterojunction power device, comprising: a first heterojunction transistor (19) formed on a substrate, the first heterojunction transistor comprising: a first Ill-nitride semiconductor region formed over the substrate, wherein the first Ill-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas of second conductivity type; a first terminal (8) operatively connected to the first Ill-nitride semiconductor region; a second terminal (9) laterally spaced from the first terminal and operatively connected to the first Ill-nitride semiconductor region; a first gate terminal (10) formed over the first Ill-nitride semiconductor region between the first terminal and the second terminal.Type: ApplicationFiled: May 7, 2020Publication date: June 30, 2022Inventors: Florin Udrea, Loizos Efthymiou, Giorgia Longobardi, Martin Arnold
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Patent number: 11336279Abstract: A device includes a heterojunction device, a unipolar power transistor operatively connected in series with said hetero junction device; an external control terminal for driving said unipolar power transistor and said heterojunction device; and an interface unit having a plurality of interface terminals. A first interface terminal is operatively connected to an active gate region of the heterojunction device and a second interface terminal is operatively connected to said external control terminal. The heterojunction device includes a threshold voltage less than a threshold voltage of the unipolar power transistor, wherein the threshold voltage of the heterojunction device is less than a blocking voltage of the unipolar power transistor.Type: GrantFiled: May 20, 2020Date of Patent: May 17, 2022Assignee: Cambridge Enterprise LimitedInventors: Florin Udrea, Loizos Efthymiou, Giorgia Longobardi, Martin Arnold
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Patent number: 11257811Abstract: The disclosure relates to a III-nitride power semiconductor based heterojunction device including a low voltage terminal, a high voltage terminal, a control terminal and an active heterojunction transistor formed on a substrate, and further including the following monolithically integrated components: voltage clamp circuit configured to limit a maximum potential that can be applied to the internal gate terminal, an on-state circuit configured to control the internal gate terminal of the active heterojunction transistor during an on-state operation, a turn-off circuit configured to control the internal gate terminal of the active heterojunction transistor during a turn-off operation and during an off-state.Type: GrantFiled: July 2, 2020Date of Patent: February 22, 2022Assignee: Cambridge Enterprise LimitedInventors: Martin Arnold, Loizos Efthymiou, David Bruce Vail, John William Findlay, Giorgia Longobardi, Florin Udrea
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Patent number: 11217687Abstract: The disclosure relates to power semiconductor devices in GaN technology. The disclosure proposes an integrated auxiliary gate terminal (15) and a pulldown network to achieve a normally-off (E-Mode) GaN transistor with threshold voltage higher than 2V, low gate leakage current and enhanced switching performance. The high threshold voltage GaN transistor has a high-voltage active GaN device (205) and a low-voltage auxiliary GaN device (210) wherein the high-voltage GaN device has the gate connected to the source of the integrated auxiliary low-voltage GaN transistor and the drain being the external high-voltage drain terminal and the source being the external source terminal, while the low-voltage auxiliary GaN transistor has the gate (first auxiliary electrode) connected to the drain (second auxiliary electrode) functioning as an external gate terminal.Type: GrantFiled: July 13, 2018Date of Patent: January 4, 2022Assignee: CAMBRIDGE ENTERPRISE LIMITEDInventors: Florin Udrea, Loizos Efthymiou, Giorgia Longobardi
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Patent number: 11211481Abstract: A heterojunction device, includes a substrate; a III-nitride semiconductor region located longitudinally above or over the substrate and including a heterojunction having a two-dimensional carrier gas; first and second laterally spaced terminals operatively connected to the semiconductor; a gate structure of first conductivity type located above or longitudinally over the semiconductor region and laterally spaced between the first and second terminals; a control gate terminal operatively connected to the gate structure, a potential applied to the control gate terminal modulates and controls a current flow through the carrier gas between the terminals, the carrier gas being a second conductivity type; an injector of carriers of the first conductivity type laterally spaced away from the second terminal; and a floating contact layer located over the carrier gas and laterally spaced away from the second terminal and operatively connected to the injector and the semiconductor region.Type: GrantFiled: January 13, 2020Date of Patent: December 28, 2021Assignee: CAMBRIDGE GAN DEVICES LIMITEDInventors: Florin Udrea, Loizos Efthymiou, Giorgia Longobardi
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Publication number: 20210335781Abstract: Power semiconductor devices in GaN technology include an integrated auxiliary (double) gate terminal and a pulldown network to achieve a normally-off (E-Mode) GaN transistor with threshold voltage higher than 2V, low gate leakage current and enhanced switching performance. The high threshold voltage GaN transistor has a high-voltage active GaN device and a low-voltage auxiliary GaN device wherein the high-voltage GaN device has the gate connected to the source of the integrated auxiliary low-voltage GaN transistor and the drain being the external high-voltage drain terminal and the source being the external source terminal, while the low-voltage auxiliary GaN transistor has the gate (first auxiliary electrode) connected to the drain (second auxiliary electrode) functioning as an external gate terminal.Type: ApplicationFiled: June 17, 2021Publication date: October 28, 2021Inventors: Martin Arnold, Loizos Efthymiou, Florin Udrea, Giorgia Longobardi, John William Findlay
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Patent number: 11081578Abstract: We disclose herein a depletion mode III-nitride semiconductor based heterojunction device, comprising: a substrate; a III-nitride semiconductor region formed over the substrate, wherein the III-nitride semiconductor region comprises a heterojunction comprising at least one two-dimensional carrier gas of second conductivity type; a first terminal operatively connected to the III-nitride semiconductor region; a second terminal laterally spaced from the first terminal in a first dimension and operatively connected to the III-nitride semiconductor region; at least two highly doped semiconductor regions of a first conductivity type formed over the III-nitride semiconductor region, the at least two highly doped semiconductor regions being formed between the first terminal and the second terminal; and a gate terminal formed over the at least two highly doped semiconductor regions; wherein the at least two highly doped semiconductor regions are spaced from each other in a second dimension.Type: GrantFiled: May 7, 2019Date of Patent: August 3, 2021Assignee: CAMBRIDGE GAN DEVICES LIMITEDInventors: Florin Udrea, Loizos Efthymiou, Giorgia Longobardi, Martin Arnold