Patents by Inventor Lokesh Johri

Lokesh Johri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8990181
    Abstract: A method for transferring data between a host device and an external device is described. The external device has FAT32 file system. The method accepts parameters for an incoming data file from the host device. Further, the method allocates memory blocks for the incoming file data on the external device based on the parameters and indexes the allocated memory blocks on a memory index table to create a file footprint. The method reads the memory index table to identify the file footprint and receives the incoming file data from the host device.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: March 24, 2015
    Assignee: Standard Microsystems Corporation
    Inventors: Lokesh Johri, Sasikala Divakaruni, Andrew Bartlett, Richard W. Holbrook
  • Publication number: 20120072401
    Abstract: A method for transferring data between a host device and an external device is described. The external device has FAT32 file system. The method accepts parameters for an incoming data file from the host device. Further, the method allocates memory blocks for the incoming file data on the external device based on the parameters and indexes the allocated memory blocks on a memory index table to create a file footprint. The method reads the memory index table to identify the file footprint and receives the incoming file data from the host device.
    Type: Application
    Filed: September 16, 2010
    Publication date: March 22, 2012
    Applicant: STANDARD MICROSYSTEMS CORPORATION
    Inventors: LOKESH JOHRI, SASIKALA DIVAKARUNI, ANDREW BARTLETT, RICHARD W. HOLBROOK
  • Patent number: 7711524
    Abstract: A method and system generate a boundary of a Schmoo plot. In accord with the method, a plurality of seed points having a resolution that is less than or equal to ½ the acquisition resolution indicated by a smoothness of a representative Schmoo boundary are selected. A coarse boundary search is performed to identify a plurality of test points that are within an acquisition resolution of the boundary. The test points that comprise the coarse boundary are interpolated to produce a fine estimate of the boundary.
    Type: Grant
    Filed: December 19, 2005
    Date of Patent: May 4, 2010
    Assignee: Verigy (Singapore) Pte. Ltd.
    Inventors: Lokesh Johri, Kaushik Ghosh, Ben Rogel-Favila
  • Patent number: 7530034
    Abstract: A method and apparatus for defining a circuit operation, such as a charged particle beam operation to perform a circuit edit and define a probe point. Circuit operation definition is performed in a front-end environment with access to integrated circuit computer aided design tools providing logic level and layout level information concerning the integrated circuit. The front-end environment incorporates circuit operation optimization methods to identify optimal locations for a circuit operation. A back-end environment, such as a charged particle tool computing platform, is adapted to receive one or more files, which may include a truncated layout file with circuit operation location information, for use in further defining a circuit operation and/or performing the circuit operation.
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: May 5, 2009
    Assignee: DCG Systems, Inc.
    Inventors: Martin Betz, Lokesh Johri, Rajesh Jain, Theodore R. Lundquist, Tamal Basu, Saurabh Gupta, Jagadish Narayana Gade
  • Publication number: 20070156352
    Abstract: A method and system generate a boundary of a Schmoo plot, comprising selecting a plurality of seed points having a resolution that is less than or equal to ½ the acquisition resolution indicated by a smoothness of a representative Schmoo boundary, performing a coarse boundary search to identify a plurality of test points that are within an acquisition resolution of the boundary, and interpolating the test points that comprise the coarse boundary to produce a fine estimate of the boundary.
    Type: Application
    Filed: December 19, 2005
    Publication date: July 5, 2007
    Inventors: Lokesh Johri, Kaushik Ghosh, Ben Rogel-Favila
  • Patent number: 7230240
    Abstract: A charged particle beam system and scanning control method capable of imaging, and possibly editing, a device under test (DUT). The charged particle beam system contains a charged particle beam generation unit, such as a focused ion beam (FIB) column, which emits a charged particle beam onto the DUT. Also included is a scan controller arrangement implementing a finite state machine to control the application of the charged particle beam onto the DUT according to a plurality of scanning control parameters. The scanning control parameters may describe one or more scan regions that are rectangular in shape. Further, the parameters may describe one or more scan regions describing other shapes by way of a bit-map. Similarly, a method for controlling the scanning of a charged particle beam that involves obtaining a set of scanning control parameters, and then directing the charged particle beam as specified by the scanning control parameters by way of a finite state machine, is disclosed.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: June 12, 2007
    Assignee: Credence Systems Corporation
    Inventors: James Siebert, Lokesh Johri, Dennis McCarty, Simon Voong, Madhumita Sengupta, Hui Wang
  • Publication number: 20060261043
    Abstract: A method and apparatus for defining a circuit operation, such as a charged particle beam operation to perform a circuit edit and define a probe point. Circuit operation definition is performed in a front-end environment with access to integrated circuit computer aided design tools providing logic level and layout level information concerning the integrated circuit. The front-end environment incorporates circuit operation optimization methods to identify optimal locations for a circuit operation. A back-end environment, such as a charged particle tool computing platform, is adapted to receive one or more files, which may include a truncated layout file with circuit operation location information, for use in further defining a circuit operation and/or performing the circuit operation.
    Type: Application
    Filed: February 27, 2006
    Publication date: November 23, 2006
    Applicant: Credence Systems Corporation
    Inventors: Martin Betz, Lokesh Johri, Rajesh Jain, Theodore Lundquist, Tamal Basu, Saurabh Gupta, Jagadish Narayana Gade
  • Patent number: 7115426
    Abstract: A method for utilizing interference fringe patterns generated when milling a trench through a semiconductor substrate by a method such as FIB milling, to determine and optimize the thickness uniformity of the trench bottom. The interference fringes may be mapped and the mapping used to direct the FIB milling to those regions which are thicker to correct observed non-uniformities in the trench floor thickness by varying the pixel dwell time across the milled area. The interference fringe mapping may be used to develop computerized contour lines to automate the pixel dwell time variations as described above, for correcting non-uniformities in the trench floor thickness. The method may be applied to applications other than trench formation for backside editing, such as monitoring progress in forming a milled object.
    Type: Grant
    Filed: January 7, 2005
    Date of Patent: October 3, 2006
    Assignee: Credence Systems Corporation
    Inventors: Erwan Le Roy, Patricia Le Coupanec, Theodore R. Lundquist, William B. Thompson, Mark A. Thompson, Lokesh Johri
  • Publication number: 20060043312
    Abstract: A charged particle beam system and scanning control method capable of imaging, and possibly editing, a device under test (DUT). The charged particle beam system contains a charged particle beam generation unit, such as a focused ion beam (FIB) column, which emits a charged particle beam onto the DUT. Also included is a scan controller arrangement implementing a finite state machine to control the application of the charged particle beam onto the DUT according to a plurality of scanning control parameters. The scanning control parameters may describe one or more scan regions that are rectangular in shape. Further, the parameters may describe one or more scan regions describing other shapes by way of a bit-map. Similarly, a method for controlling the scanning of a charged particle beam that involves obtaining a set of scanning control parameters, and then directing the charged particle beam as specified by the scanning control parameters by way of a finite state machine, is disclosed.
    Type: Application
    Filed: August 31, 2004
    Publication date: March 2, 2006
    Inventors: James Siebert, Lokesh Johri, Dennis McCarty, Simon Voong, Madhumita Sengupta, Hui Wang
  • Publication number: 20060030064
    Abstract: A method for utilizing interference fringe patterns generated when milling a trench through a semiconductor substrate by a method such as FIB milling, to determine and optimize the thickness uniformity of the trench bottom. The interference fringes may be mapped and the mapping used to direct the FIB milling to those regions which are thicker to correct observed non-uniformities in the trench floor thickness by varying the pixel dwell time across the milled area. The interference fringe mapping may be used to develop computerized contour lines to automate the pixel dwell time variations as described above, for correcting non-uniformities in the trench floor thickness. The method may be applied to applications other than trench formation for backside editing, such as monitoring progress in forming a milled object.
    Type: Application
    Filed: January 7, 2005
    Publication date: February 9, 2006
    Inventors: Erwan Roy, Patricia Coupanec, Theodore Lundquist, William Thompson, Mark Thompson, Lokesh Johri