Abstract: An integrated circuit (IC) may include a set of instruction list engines (ILEs) that execute in parallel, where each ILE stores a subset of a set of instructions for processing a header of a frame, and where each ILE generates an ILE result based on executing the subset of the set of instructions. The IC may include a circuit to determine a result of parsing the header of the frame based on merging ILE results generated by the set of ILEs.

Abstract: A dual-mode Reed-Solomon decoder is configured to perform error correction for two different encoding schemes. The decoder includes a syndrome calculator block, a key equation solver block, a polynomial evaluation block, and an error correction block. The syndrome calculator block receives encoded input data and calculates syndromes, with the number of calculated syndromes based on the selected decoding mode. The key equation solver block calculates an error locator polynomial and an error evaluator polynomial for the encoded input data, with the degree of the polynomials based on the selected decoding mode. The polynomial evaluation block identifies error locations and magnitudes in the encoded data, with an array of constants input to the block based on the selected decoding mode. The error correction block decodes the encoded input data based on the identified error locations and error magnitudes.

Abstract: A dual-mode Reed-Solomon decoder is configured to perform error correction for two different encoding schemes. The decoder includes a syndrome calculator block, a key equation solver block, a polynomial evaluation block, and an error correction block. The syndrome calculator block receives encoded input data and calculates syndromes, with the number of calculated syndromes based on the selected decoding mode. The key equation solver block calculates an error locator polynomial and an error evaluator polynomial for the encoded input data, with the degree of the polynomials based on the selected decoding mode. The polynomial evaluation block identifies error locations and magnitudes in the encoded data, with an array of constants input to the block based on the selected decoding mode. The error correction block decodes the encoded input data based on the identified error locations and error magnitudes.

Abstract: Low-power, easily scalable architectures for high-speed data handling are critical to modern circuits and systems. Successful architectures must provide efficient data storage and efficient/flexible data retrieval with low power consumption. Data encoding, including that achieved with turbo codes, have data streams split into a sequence of even and odd data bits. These bits are written into multiple single-port memories so that the writing alternates between memories. Scheduling for the reading and writing is performed to avoid conflicts and give priority to the read operations.