Patents by Inventor Lokesh Kumar Saini

Lokesh Kumar Saini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Circuit Architecture in Multi-Dimensional Monolithic Structure
    Publication number: 20230335537
    Abstract: Various implementations described herein are related to a device having a multi-transistor structure for use in circuit architecture. The multi-transistor structure may have a multi-transistor stack of at least one of N-type transistors or P-type transistors that are arranged in a multi-device stack configuration. Also, a physical layout of the multi-device stack configuration may provide a common-centroid configuration for process mismatch cancellation in at least one of the X-Y-Z axes.
    Type: Application
    Filed: April 15, 2022
    Publication date: October 19, 2023
    Inventors: Lokesh Kumar Saini, Amit Chhabra, Valerio Lanieri
  • Write operation scheme for SRAM
    Patent number: 10199094
    Abstract: A circuit includes a memory cell with a bitline. A pulldown nMOSFET has a gate terminal connected to an output port of a logic gate, and a drain terminal connected to the first bitline. A write select line is connected to a second input port of the logic gate. A pullup pMOSFET has a gate terminal connected to the write select line, and a drain terminal connected to the bitline.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: February 5, 2019
    Assignee: ARM Limited
    Inventors: Ankur Goel, Saikat Kumar Banik, Lokesh Kumar Saini, Vivek Asthana
  • Write Operation Scheme for SRAM
    Publication number: 20180358086
    Abstract: A circuit includes a memory cell with a bitline. A pulldown nMOSFET has a gate terminal connected to an output port of a logic gate, and a drain terminal connected to the first bitline. A write select line is connected to a second input port of the logic gate. A pullup pMOSFET has a gate terminal connected to the write select line, and a drain terminal connected to the bitline.
    Type: Application
    Filed: June 9, 2017
    Publication date: December 13, 2018
    Inventors: Ankur Goel, Saikat Kumar Banik, Lokesh Kumar Saini, Vivek Asthana