Patents by Inventor Lokesh M. Gupta

Lokesh M. Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11940920
    Abstract: Provided are a computer program product, system, and method for determining tracks to prestage into cache from a storage. Information is provided related to determining tracks to prestage from the storage to the cache in a stage group of sequential tracks including a trigger track comprising a track number in the stage group at which to start prestaging tracks and Input/Output (I/O) activity information to a machine learning module. A new trigger track in the stage group at which to start prestaging tracks is received from the machine learning module having processed the provided information. The trigger track is set to the new trigger track. Tracks are prestaged in response to processing an access request to the trigger track in the stage group.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: March 26, 2024
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Matthew G. Borlick, Kevin J. Ash
  • Publication number: 20230306111
    Abstract: Provided are a computer program product, system, and method for using trap cache segments to detect malicious processes. A trap cache segment to the cache for data in the storage and indicated as a trap cache segment. Cache segments are added to the cache having data from the storage that are not indicated as trap cache segments. A memory function call from a process executing in the computer system reads data from a region of a memory device to output the read data to a buffer of the memory device. A determination is made as to whether the region of the memory device includes the trap cache segment. The memory function call is blocked and the process is treated as a potentially malicious process in response to determining that the region includes the trap cache segment.
    Type: Application
    Filed: May 30, 2023
    Publication date: September 28, 2023
    Inventors: Brian A. Rinaldi, Clint A. Hardy, Lokesh M. Gupta, Kevin J. Ash
  • Patent number: 11755735
    Abstract: Provided are a computer program product, system, and method for determining a frequency at which to execute trap code in an execution path of a process executing a program to generate a trap address range to detect potential malicious code. Trap code is executed in response to processing a specified type of command in application code to allocate a trap address range used to detect potentially malicious code. A determination is whether to modify a frequency of executing the trap code in response to processing a specified type of command. The frequency of executing the trap code is modified in response to processing the specified type of command in response to determining to determining to modify the frequency of executing the trap code.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: September 12, 2023
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Matthew G. Borlick, Trung N. Nguyen, Micah Robison
  • Patent number: 11704209
    Abstract: Provided are a computer program product, system, and method for using a track format code in a cache control block for a track in a cache to process read and write requests to the track in the cache. A track format table associates track format codes with track format metadata. A determination is made as to whether the track format table has track format metadata matching track format metadata of a track staged into the cache. A determination is made as to whether a track format code from the track format table for the track format metadata in the track format table matches the track format metadata of the track staged. A cache control block for the track being added to the cache is generated including the determined track format code when the track format table has the matching track format metadata.
    Type: Grant
    Filed: February 2, 2022
    Date of Patent: July 18, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kyler A. Anderson, Kevin J. Ash, Lokesh M. Gupta, Matthew J. Kalos, Beth A. Peterson
  • Patent number: 11681799
    Abstract: Provided are a computer program product, system, and method for using trap cache segments to detect malicious processes. A trap cache segment to the cache for data in the storage and indicated as a trap cache segment. Cache segments are added to the cache having data from the storage that are not indicated as trap cache segments. A memory function call from a process executing in the computer system reads data from a region of a memory device to output the read data to a buffer of the memory device. A determination is made as to whether the region of the memory device includes the trap cache segment. The memory function call is blocked and the process is treated as a potentially malicious process in response to determining that the region includes the trap cache segment.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: June 20, 2023
    Assignee: INTERNATIONAL BUSINES MACHINES CORPORATION
    Inventors: Brian A. Rinaldi, Clint A. Hardy, Lokesh M. Gupta, Kevin J. Ash
  • Patent number: 11663129
    Abstract: Provided are a computer program product, system, and method for determining tracks to prestage into cache from a storage. Information is provided related to determining tracks to prestage from the storage to the cache in a stage group of sequential tracks including a trigger track comprising a track number in the stage group at which to start prestaging tracks and Input/Output (I/O) activity information to a machine learning module. A new trigger track in the stage group at which to start prestaging tracks is received from the machine learning module having processed the provided information. The trigger track is set to the new trigger track. Tracks are prestaged in response to processing an access request to the trigger track in the stage group.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: May 30, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Matthew G. Borlick, Kevin J. Ash
  • Patent number: 11663144
    Abstract: A method for improving cache hit ratios for selected storage elements within a storage system includes storing, in a cache of a storage system, non-favored storage elements and favored storage elements. The favored storage elements are retained in the cache longer than the non-favored storage elements. The method maintains a first LRU list containing entries associated with non-favored storage elements and designating an order in which the non-favored storage elements are evicted from the cache, and a second LRU list containing entries associated with favored storage elements and designating an order in which the favored storage elements are evicted from the cache. The method periodically scans the first LRU list for non-favored storage elements that have changed to favored storage elements, and the second LRU list for favored storage elements that have changed to non-favored storage elements. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: May 30, 2023
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kevin J. Ash, Matthew G. Borlick, Beth A. Peterson
  • Patent number: 11651070
    Abstract: Provided are a computer program product, system, and method for detecting a security breach in a system managing access to a storage. Process Input/Output (I/O) activity by a process accessing data in a storage is monitored. A determination is made of a characteristic of the data subject to the I/O activity from the process. A determination is made as to whether a characteristic of the process I/O activity as compared to the characteristic of the data satisfies a condition. The process initiating the I/O activity is characterized as a suspicious process in response to determining that the condition is satisfied. A security breach is indicated in response to characterizing the process as the suspicious process.
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: May 16, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew G. Borlick, Lokesh M. Gupta
  • Patent number: 11620226
    Abstract: A method to prevent starvation of non-favored volumes in cache is disclosed. In one embodiment, such a method includes storing, in a cache of a storage system, non-favored storage elements and favored storage elements. A cache demotion algorithm is used to retain the favored storage elements in the cache longer than the non-favored storage elements. The method designates a maximum amount of storage space that the favored storage elements are permitted to consume in the cache. In preparation to free storage space in the cache, the method determines whether an amount of storage space consumed by the favored storage elements in the cache has reached the maximum amount. If so, the method frees storage space in the cache by demoting favored storage elements. If not, the method frees storage space in the cache in accordance with the cache demotion algorithm. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: February 9, 2020
    Date of Patent: April 4, 2023
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kevin J. Ash, Matthew G. Borlick, Beth A. Peterson
  • Patent number: 11620219
    Abstract: In one embodiment, storage drive dependent track removal processing logic performs destage tasks for tracks cached in a cache as a function of whether the storage drive is classified as a fast class or as slow class of storage drives, for example. In one embodiment, a destage task configured for a slow class storage drive, transfers an entry for a track selected for destaging from a main cache list to a wait cache list to await destaging to the slow class drive. A destage task configured for a fast class storage drive allows the cache list entry for the selected track to remain on the main cache list while the selected track is being destaged to the fast class storage drive, thereby bypassing the transfer of the entry to a wait cache list. Other features and aspects may be realized, depending upon the particular application.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: April 4, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta, Trung N. Nguyen
  • Patent number: 11561905
    Abstract: A minimum retention time in cache is indicated for a first plurality of tracks, where no minimum retention time is indicated for a second plurality of tracks. A cache management application demotes a track of the first plurality of tracks from the cache, in response to determining that the track is a least recently used (LRU) track in a LRU list of tracks in the cache and the track has been in the cache for a time that exceeds the minimum retention time.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: January 24, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Joseph Hayward, Matthew G. Borlick
  • Patent number: 11550732
    Abstract: A method for maintaining statistics for data elements in a cache is disclosed. The method maintains a heterogeneous cache comprising a higher performance portion and a lower performance portion. The method maintains, within the lower performance portion, a ghost cache containing statistics for data elements that are currently contained in the heterogeneous cache, and data elements that have been demoted from the heterogeneous cache within a specified time interval. The method calculates a size of the ghost cache based on an amount of frequently accessed data that is stored in backend storage volumes behind the heterogeneous cache. The method alters the size of the ghost cache as the amount of frequently accessed data changes. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: February 22, 2020
    Date of Patent: January 10, 2023
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew G. Borlick
  • Patent number: 11520515
    Abstract: A computational device generates a point in time copy of one or more regions of a time locked data set, in response to receiving one or more I/O operations directed to the time locked data set. The one or more I/O operations are performed on the point in time copy of the one or more regions of the time locked data set, in response to generating the point in time copy of the one or more regions of the time locked data set.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: December 6, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew G. Borlick, Lokesh M. Gupta
  • Patent number: 11520631
    Abstract: A plurality of processing entities in which a plurality of tasks are executed are maintained. Memory access patterns are determined for each of the plurality of tasks by dividing a memory associated with the plurality of processing entities into a plurality of memory regions, and for each of the plurality of tasks, determining how many memory accesses take place in each of the memory regions, by incrementing a counter associated with each memory region in response to a memory access. Each of the plurality of tasks are allocated among the plurality of processing entities, based on the determined memory access patterns for each of the plurality of tasks.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: December 6, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew G. Borlick, Lokesh M. Gupta, Trung N. Nguyen
  • Patent number: 11494309
    Abstract: A list of a first type of tracks in a cache is generated. A list of a second type of tracks in the cache is generated, wherein I/O operations are completed relatively faster to the first type of tracks than to the second type of tracks. A determination is made as to whether to demote a track from the list of the first type of tracks or from the list of the second type of tracks.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: November 8, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kyler A. Anderson, Kevin J. Ash, Lokesh M. Gupta
  • Patent number: 11461112
    Abstract: Provided are a computer program product, system, and method for determining feature settings for code to deploy to a system by training a machine learning module. A determination is made of an outcome of running system code on a system having configuration settings and feature settings of features in the system to enable or disable in response to the outcome. A machine learning module is trained to produce the feature settings indicating to enable or disable the features in response to input comprising the configuration settings of the system.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: October 4, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew G. Borlick, Lokesh M. Gupta, Matthew R. Craig, Micah Robison
  • Patent number: 11461242
    Abstract: A computational device receives indications of a minimum retention time and a maximum retention time in cache for a first plurality of tracks, wherein no indications of a minimum retention time or a maximum retention time in the cache are received for a second plurality of tracks. A cache management application demotes a track of the first plurality of tracks from the cache, in response to determining that the track is a least recently used (LRU) track in a LRU list of tracks in the cache and the track has been in the cache for a time that exceeds the minimum retention time. The cache management application demotes the track of the first plurality of tracks, in response to determining that the track has been in the cache for a time that exceeds the maximum retention time.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: October 4, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh M. Gupta, Joseph Hayward, Kyler A. Anderson, Matthew G. Borlick
  • Patent number: 11455003
    Abstract: A computational device receives an input/output (I/O) operation directed to a data set. In response to determining that there is a time lock on the data set, a determination is made as to whether a clock of the computational device is providing a correct time. In response to determining that the clock of the computational device is not providing the correct time, the I/O operation is restricted from accessing the data set. In response to determining that the clock of the computational device is providing the correct time, a determination is made from one or more time entries of the time lock whether to provide the I/O operation with access to the data set.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: September 27, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew G. Borlick, Lokesh M. Gupta
  • Patent number: 11442826
    Abstract: A method for reducing incidents of data loss in redundant arrays of independent disks (RAIDs) having the same RAID level is disclosed. In one embodiment, such a method identifies, in a data storage environment, a set of RAIDs having a common RAID level. The method also identifies, in the set of RAIDs, higher risk storage drives having a failure risk above a threshold and lower risk storage drives having a failure risk below the threshold. The method swaps, within the RAIDs, higher risk storage drives with lower risk storage drives to more evenly distribute higher risk storage drives across the RAIDs. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: June 15, 2019
    Date of Patent: September 13, 2022
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Matthew G. Borlick, Karl A. Nielsen, Clint A. Hardy, Brian A. Rinaldi
  • Patent number: 11422948
    Abstract: A computational device receives an indication of a minimum retention time in a cache for a plurality of tracks of an application. In response to determining that tracks of the application that are stored in the cache exceed a predetermined threshold in the cache, the computational device demotes one or more tracks of the application from the cache even though a minimum retention time in cache has been indicated for the one or more tracks of the application, while performing least recently used (LRU) based replacement of tracks in the cache.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: August 23, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh M. Gupta, Roger G. Hathorn, Joseph Hayward, Matthew G. Borlick