Abstract: Techniques for generating machine learning training data which corresponds to one or more downstream tasks are disclosed. In one example, a computer implemented method comprises generating one or more synthetic data instances for training a machine learning model, and determining a value of respective ones of the one or more synthetic data instances with respect to at least one task. One or more additional synthetic data instances for training the machine learning model are generated based at least in part on the values of the respective ones of the one or more synthetic data instances.

Abstract: In one embodiment, a processor includes at least one core to execute instructions, one or more thermal sensors associated with the at least one core, and a power controller coupled to the at least one core. The power controller has a control logic to receive temperature information regarding the processor and dynamically determine a maximum allowable average power limit based at least in part on the temperature information. The control logic may further maintain a static maximum base operating frequency of the processor regardless of a value of the temperature information. Other embodiments are described and claimed.

Abstract: This disclosure relates to method and system for dynamically identifying change in customer behaviour and providing appropriate personalized recommendations. The method includes, for each of a plurality of transactions and for each of one or more customers, generating customer behaviour data based on customer transaction data and pre-defined product segmentation data; generating a state-action-reward pair based on customer transaction data and the pre-defined product segmentation data; and generating state-behaviour mapping data based on customer behaviour data and the state-action-reward pair.

Abstract: In one embodiment, a processor includes at least one core to execute instructions, one or more thermal sensors associated with the at least one core, and a power controller coupled to the at least one core. The power controller has a control logic to receive temperature information regarding the processor and dynamically determine a maximum allowable average power limit based at least in part on the temperature information. The control logic may further maintain a static maximum base operating frequency of the processor regardless of a value of the temperature information. Other embodiments are described and claimed.

Abstract: In one embodiment, a processor includes at least one core to execute instructions, one or more thermal sensors associated with the at least one core, and a power controller coupled to the at least one core. The power controller has a control logic to receive temperature information regarding the processor and dynamically determine a maximum allowable average power limit based at least in part on the temperature information. The control logic may further maintain a static maximum base operating frequency of the processor regardless of a value of the temperature information. Other embodiments are described and claimed.

Abstract: In one embodiment, a processor includes at least one core to execute instructions, one or more thermal sensors associated with the at least one core, and a power controller coupled to the at least one core. The power controller has a control logic to receive temperature information regarding the processor and dynamically determine a maximum allowable average power limit based at least in part on the temperature information. The control logic may further maintain a static maximum base operating frequency of the processor regardless of a value of the temperature information. Other embodiments are described and claimed.

Abstract: In one embodiment, a processor includes at least one core to execute instructions, one or more thermal sensors associated with the at least one core, and a power controller coupled to the at least one core. The power controller has a control logic to receive temperature information regarding the processor and dynamically determine a maximum allowable average power limit based at least in part on the temperature information. The control logic may further maintain a static maximum base operating frequency of the processor regardless of a value of the temperature information. Other embodiments are described and claimed.

Abstract: A processor may include a core and an uncore area. The power consumed by the core area may be controlled by controlling the Cdyn of the processor such that the Cdyn is within an allowable Cdyn value irrespective of the application being processed by the core area. The power management technique includes measuring digital activity factor (DAF), monitoring architectural and data activity levels, and controlling power consumption by throttling the instructions based on the activity levels. As a result of throttling the instructions, throttling may be implemented in 3rd droop and thermal design point (TDP). Also, the idle power consumed by the uncore area while the core area is in deep power saving states may be reduced by varying the reference voltage VR and the VP provided to the uncore area. As a result, the idle power consumed by the uncore area may be reduced.

Abstract: A processor may include a core and an uncore area. The power consumed by the core area may be controlled by controlling the dynamic capacitance of the processor such that the dynamic capacitance is within an allowable dynamic capacitance value irrespective of the application being processed by the core area. The power management technique includes measuring digital activity factor (DAF), monitoring architectural and data activity levels, and controlling power consumption by throttling the instructions based on the activity levels. As a result of throttling the instructions, throttling may be implemented in 3rd droop and thermal design point (TDP). Also, the idle power consumed by the uncore area while the core area is in deep power saving states may be reduced by varying the reference voltage VR and the VP provided to the uncore area. As a result, the idle power consumed by the uncore area may be reduced.

Abstract: A processor may include a core and an uncore area. The power consumed by the core area may be controlled by controlling the Cdyn of the processor such that the Cdyn is within an allowable Cdyn value irrespective of the application being processed by the core area. The power management technique includes measuring digital activity factor (DAF), monitoring architectural and data activity levels, and controlling power consumption by throttling the instructions based on the activity levels. As a result of throttling the instructions, throttling may be implemented in 3rd droop and thermal design point (TDP). Also, the idle power consumed by the uncore area while the core area is in deep power saving states may be reduced by varying the reference voltage VR and the VP provided to the uncore area. As a result, the idle power consumed by the uncore area may be reduced.

Abstract: A processor may include a core and an uncore area. The power consumed by the core area may be controlled by controlling the Cdyn of the processor such that the Cdyn is within an allowable Cdyn value irrespective of the application being processed by the core area. The power management technique includes measuring digital activity factor (DAF), monitoring architectural and data activity levels, and controlling power consumption by throttling the instructions based on the activity levels. As a result of throttling the instructions, throttling may be implemented in 3rd droop and thermal design point (TDP). Also, the idle power consumed by the uncore area while the core area is in deep power saving states may be reduced by varying the reference voltage VR and the VP provided to the uncore area. As a result, the idle power consumed by the uncore area may be reduced.