Patents by Inventor Lokesh Subramany

Lokesh Subramany has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10121711
    Abstract: Approaches for providing a substrate having a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. Specifically, the FinFET device comprises a finned substrate, and a planar metrology pad formed on the substrate adjacent the fins in a metrology measurement area of the FinFET device. Processing steps include forming a first hardmask over the substrate, forming a photoresist over a portion of the first hardmask in the metrology measurement area of the FinFET device, removing the first hardmask in an area adjacent the metrology measurement area remaining exposed following formation of the photoresist, patterning a set of openings in the substrate to form the set of fins in the FinFET device in the area adjacent the metrology measurement area, depositing an oxide layer over the FinFET device, and planarizing the FinFET device to form the planar metrology pad in the metrology measurement area.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: November 6, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sipeng Gu, Xiang Hu, Alok Vaid, Lokesh Subramany, Akshey Sehgal
  • Patent number: 9281249
    Abstract: Measurement of thickness of layers of a circuit structure is obtained, where the thickness of the layers is measured using an optical critical dimension (OCD) measurement technique, and the layers includes a high-k layer and an interfacial layer. Measurement of thickness of the high-k layer is separately obtained, where the thickness of the high-k layer is measured using a separate measurement technique from the OCD measurement technique. The separate measurement technique provides greater decoupling, as compared to the OCD measurement technique, of a signal for thickness of the high-k layer from a signal for thickness of the interfacial layer of the layers. Characteristics of the circuit structure, such as a thickness of the interfacial layer, are ascertained using, in part, the separately obtained thickness measurement of the high-k layer.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: March 8, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Alok Vaid, Abner Bello, Sipeng Gu, Lokesh Subramany, Xiang Hu, Akshey Sehgal
  • Publication number: 20150348913
    Abstract: Approaches for providing a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. A previously deposited amorphous carbon layer can be removed from over a mandrel that has been previously formed on a subset of a substrate, such as using a photoresist. A pad hardmask can be formed over the mandrel on the subset of the substrate. This formation results in the subset of the substrate having the pad hardmask covering the mandrel thereon and the remainder of the substrate having the amorphous carbon layer covering the mandrel thereon. This amorphous carbon layer can be removed from over the mandrel on the remainder of the substrate, allowing a set of fins to be formed therein while the amorphous carbon layer keeps the set of fins from being formed in the portion of the substrate that it covers.
    Type: Application
    Filed: August 4, 2015
    Publication date: December 3, 2015
    Applicant: Globalfoundries Inc.
    Inventors: Xiang Hu, Lokesh Subramany, Alok Vaid, Sipeng Gu, Akshey Sehgal
  • Publication number: 20150340296
    Abstract: Approaches for providing a substrate having a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. Specifically, the FinFET device comprises a finned substrate, and a planar metrology pad formed on the substrate adjacent the fins in a metrology measurement area of the FinFET device. Processing steps include forming a first hardmask over the substrate, forming a photoresist over a portion of the first hardmask in the metrology measurement area of the FinFET device, removing the first hardmask in an area adjacent the metrology measurement area remaining exposed following formation of the photoresist, patterning a set of openings in the substrate to form the set of fins in the FinFET device in the area adjacent the metrology measurement area, depositing an oxide layer over the FinFET device, and planarizing the FinFET device to form the planar metrology pad in the metrology measurement area.
    Type: Application
    Filed: August 3, 2015
    Publication date: November 26, 2015
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Sipeng Gu, Xiang Hu, Alok Vaid, Lokesh Subramany, Akshey Sehgal
  • Patent number: 9177873
    Abstract: Methods and systems are provided for fabricating and measuring physical features of a semiconductor device structure. An exemplary method of fabricating a semiconductor device structure involves obtaining raw measurement data for a wafer of semiconductor material from a metrology tool and adjusting a measurement model utilized by a metrology tool based at least in part on the raw measurement data and a value for a design parameter. The wafer has that value for the design parameter and an attribute of the semiconductor device structure fabricated thereon, wherein the measurement model is utilized by the metrology tool to convert the raw measurement data to a measurement value for the attribute.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: November 3, 2015
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Alok Vaid, Carsten Hartig, Lokesh Subramany
  • Patent number: 9129905
    Abstract: Approaches for providing a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. A previously deposited amorphous carbon layer can be removed from over a mandrel that has been previously formed on a subset of a substrate, such as using a photoresist. A pad hardmask can be formed over the mandrel on the subset of the substrate. This formation results in the subset of the substrate having the pad hardmask covering the mandrel thereon and the remainder of the substrate having the amorphous carbon layer covering the mandrel thereon. This amorphous carbon layer can be removed from over the mandrel on the remainder of the substrate, allowing a set of fins to be formed therein while the amorphous carbon layer keeps the set of fins from being formed in the portion of the substrate that it covers.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: September 8, 2015
    Assignee: GlobalFoundries Inc.
    Inventors: Xiang Hu, Lokesh Subramany, Alok Vaid, Sipeng Gu, Akshey Sehgal
  • Patent number: 9121890
    Abstract: Approaches for providing a substrate having a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. Specifically, the FinFET device comprises a finned substrate, and a planar metrology pad formed on the substrate adjacent the fins in a metrology measurement area of the FinFET device. Processing steps include forming a first hardmask over the substrate, forming a photoresist over a portion of the first hardmask in the metrology measurement area of the FinFET device, removing the first hardmask in an area adjacent the metrology measurement area remaining exposed following formation of the photoresist, patterning a set of openings in the substrate to form the set of fins in the FinFET device in the area adjacent the metrology measurement area, depositing an oxide layer over the FinFET device, and planarizing the FinFET device to form the planar metrology pad in the metrology measurement area.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: September 1, 2015
    Assignee: GlobalFoundries Inc.
    Inventors: Sipeng Gu, Xiang Hu, Alok Vaid, Lokesh Subramany, Akshey Sehgal
  • Publication number: 20150198435
    Abstract: Measurement of thickness of layers of a circuit structure is obtained, where the thickness of the layers is measured using an optical critical dimension (OCD) measurement technique, and the layers includes a high-k layer and an interfacial layer. Measurement of thickness of the high-k layer is separately obtained, where the thickness of the high-k layer is measured using a separate measurement technique from the OCD measurement technique. The separate measurement technique provides greater decoupling, as compared to the OCD measurement technique, of a signal for thickness of the high-k layer from a signal for thickness of the interfacial layer of the layers. Characteristics of the circuit structure, such as a thickness of the interfacial layer, are ascertained using, in part, the separately obtained thickness measurement of the high-k layer.
    Type: Application
    Filed: January 15, 2014
    Publication date: July 16, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Alok VAID, Abner BELLO, Sipeng GU, Lokesh SUBRAMANY, Xiang HU, Akshey SEHGAL
  • Publication number: 20150123212
    Abstract: Approaches for providing a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. A previously deposited amorphous carbon layer can be removed from over a mandrel that has been previously formed on a subset of a substrate, such as using a photoresist. A pad hardmask can be formed over the mandrel on the subset of the substrate. This formation results in the subset of the substrate having the pad hardmask covering the mandrel thereon and the remainder of the substrate having the amorphous carbon layer covering the mandrel thereon. This amorphous carbon layer can be removed from over the mandrel on the remainder of the substrate, allowing a set of fins to be formed therein while the amorphous carbon layer keeps the set of fins from being formed in the portion of the substrate that it covers.
    Type: Application
    Filed: November 4, 2013
    Publication date: May 7, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Xiang Hu, Lokesh Subramany, Alok Vaid, Sipeng Gu, Akshey Sehgal
  • Publication number: 20150115267
    Abstract: Approaches for providing a substrate having a planar metrology pad adjacent a set of fins of a fin field effect transistor (FinFET) device are disclosed. Specifically, the FinFET device comprises a finned substrate, and a planar metrology pad formed on the substrate adjacent the fins in a metrology measurement area of the FinFET device. Processing steps include forming a first hardmask over the substrate, forming a photoresist over a portion of the first hardmask in the metrology measurement area of the FinFET device, removing the first hardmask in an area adjacent the metrology measurement area remaining exposed following formation of the photoresist, patterning a set of openings in the substrate to form the set of fins in the FinFET device in the area adjacent the metrology measurement area, depositing an oxide layer over the FinFET device, and planarizing the FinFET device to form the planar metrology pad in the metrology measurement area.
    Type: Application
    Filed: October 30, 2013
    Publication date: April 30, 2015
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Sipeng Gu, Xiang Hu, Alok Vaid, Lokesh Subramany, Akshey Sehgal
  • Publication number: 20150033201
    Abstract: Methods and systems are provided for fabricating and measuring physical features of a semiconductor device structure. An exemplary method of fabricating a semiconductor device structure involves obtaining raw measurement data for a wafer of semiconductor material from a metrology tool and adjusting a measurement model utilized by a metrology tool based at least in part on the raw measurement data and a value for a design parameter. The wafer has that value for the design parameter and an attribute of the semiconductor device structure fabricated thereon, wherein the measurement model is utilized by the metrology tool to convert the raw measurement data to a measurement value for the attribute.
    Type: Application
    Filed: July 29, 2013
    Publication date: January 29, 2015
    Applicant: GLOBALFOUNDRIES, Inc.
    Inventors: Alok Vaid, Carsten Hartig, Lokesh Subramany
  • Publication number: 20140211175
    Abstract: An approach for enhancing resolution in a lithographic process (e.g., an immersion lithographic process) is provided. Specifically, a material having a high reflexive index (e.g., water) is provided on opposite sides of an objective lens. This allows a set of light rays (high intensity) to be directed/passed from a light source, through a condenser lens, over a mask, through the material positioned on one side of the objective lens, through the objective lens, through the material on the opposite side of the objective lens, and to a wafer that is then patterned. Positioning the material on both sides of the objective lens allows for improved resolution and lithographic patterning of the wafer for both on-axis illumination and off-axis illumination techniques.
    Type: Application
    Filed: January 31, 2013
    Publication date: July 31, 2014
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Lokesh Subramany, Yayi Wei