Patents by Inventor Lon-Phon Lin

Lon-Phon Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040047344
    Abstract: A method and system for providing an “Always-On” Internet device is disclosed. The Always-On Internet device can be turned on constant due to its use of low power components, while a conventional PC cannot afford to. The Internet device acts as a “hub” for all the network and peripheral connections of the PC. The Internet device can be connected to the Internet and then connected to the conventional PC. The PC's keyboard, video monitor, and mouse connections are re-directed to the Internet device, which then connects to the PC at the PC's keyboard, video and mouse connectors. The Internet device has a switching gear unit that KVM functionality and Internet Connection Sharing, the control of which is transferred between the PC and the Internet device, depending on whether the PC is on or off.
    Type: Application
    Filed: August 14, 2003
    Publication date: March 11, 2004
    Inventors: Kevin Hsunko Chan, Jeng-Feng Lee, Lon-Phon Lin
  • Patent number: 5475605
    Abstract: A computer automated logic synthesis tool performs a timing analysis during the optimization of a hardware description file including general logic expressions of a prototype circuit by minimizing a delay value for a gate network comprised of logic cells provided in a target library. Minimization occurs by modeling a gate network for a logic expression that orders the input signals into the gate network according to their input delays, and the output delays from assigned logic cells. The output delay for the assigned logic cell is based on intrinsic delays of boolean nodes in the logic cells. The delay for the gate network includes an R-C delay value for gate fan-out, based on the average R-C delay values in the target library. The logic synthesis tool is able to select from among various alternate logically equivalent gate networks, the gate network that provides the minimized timing delay.
    Type: Grant
    Filed: May 26, 1994
    Date of Patent: December 12, 1995
    Assignee: Cadence Design Systems, Inc.
    Inventor: Lon-Phon Lin
  • Patent number: D493780
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: August 3, 2004
    Inventors: Hsun-Ko Chan, Jeng-Feng Lee, Lon-Phon Lin